Hardware design exploration of fully-connected deep neural network with binary parameters

ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things

Volumn , Issue , 2016, Pages 305-306

  Kim, Jinkyu ^a   Kim, Juyeob ^a   Kim, Byungjo ^a   Lee, Miyoung ^a   Lee, Joohyun ^a  

^a Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

Author keywords

DNN; FPGA

Indexed keywords

BINS; COMPLEX NETWORKS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTERNET OF THINGS;

BINARY PARAMETERS; DEEP NEURAL NETWORKS; HARDWARE COMPLEXITY; HARDWARE DESIGN; LEARNING ACCURACY; NUMBER OF LAYERS; REFERENCE MODELING; SYNTHESIS TOOL;

HARDWARE;

EID: 85010282705     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISOCC.2016.7799799     Document Type: Conference Paper

References (5)

1. Karen Simonyan and Andrew Zisserman, "VERY DEEP CONVOLUTIONAL NETWORKS FOR LARGE-SCALE IMAGE RECOGNITION, " CoRR (2015).
2. Krizhevsky, A., Sutskever, I., and Hinton, G. E, "ImageNet classification with deep convolutional neural networks, " NIPS, pp. 1106-1114, 2012.
3. Courbariaux. M, Bengio. Y, David. J.P, "Binaryconnect: Training deep neural networks with binary weights during propagations, " In: Advances in Neural Information Processing Systems. (2015) 3105-3113.
4. Mohammad Rastegari, Vicente Ordonez, Joseph Redmon, Ali Farhadi, "XNOR-Net: ImageNet Classification Using Binary Convolutional Neural Networks, " CoRR (2016).
5. Yann LeCun, Corinna Cortes and Chistopher J.C. Burges, "THE MNIST DATABASE of handwirttern digits, "http://yann.lecun.com/exdb/mnist.