Leading-zero anticipatory logic for high-speed floating point addition

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1995, Pages 589-592

  Suzuki, Hiroaki ^a   Nakase, Yasunobu ^a   Makino, Hiroshi ^a   Morinaka, Hiroyuki ^a   Mashiko, Koichiro ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; DIGITAL ARITHMETIC; LOGIC DESIGN; MATHEMATICAL MODELS; POLES AND ZEROS; THREE DIMENSIONAL COMPUTER GRAPHICS;

HIGH SPEED FLOATING POINT ADDITION; LEADING ZERO ANTICIPATORY LOGIC;

FORMAL LOGIC;

EID: 0029234489     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)