Ultra high I/O density package: Sea of leads (SoL)

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 4428, Issue , 2001, Pages 335-339

  Bakir, M S ^a   Patel, C S ^a   Kohl, P A ^a   Martin, K P ^a   Meindl, J D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Complaint wafer level package (CWLP); Sea of leads (SoL); System on a chip (SoC)

Indexed keywords

INTEGRATED CIRCUIT MANUFACTURE; INTERCONNECTION NETWORKS; LEAD; SCANNING ELECTRON MICROSCOPY; SEMICONDUCTOR DEVICE MANUFACTURE;

COMPLIANT WAFER LEVEL PACKAGING; MECHANICAL DESIGN; SEA OF LEADS; SYSTEM ON A CHIP; ULTRA HIGH INPUT OUTPUT DENSITY PACKAGE;

ELECTRONICS PACKAGING;

EID: 0034833653     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Low cost high density compliant wafer level package
2. Cost analysis of compliant wafer level packages
3. An integrated architecture for global interconnects in a gigascale system-on-a-chip (GSoC)