The effects of thermal processing on CMOS device performance

9th International Conference on Advanced Thermal Processing of Semiconductors, RTP 2001

Volumn , Issue , 2001, Pages 62-67

  Machala, C F ^a   Yang, S H ^a   Bowen, C ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DOPING (ADDITIVES); RECONFIGURABLE HARDWARE;

CMOS DEVICES; CMOS SCALING; DEVICE PERFORMANCE; GATE LENGTH; GATE OXIDE; POLY-DEPLETION; PROCESS DEVELOPMENT; SOURCE/DRAIN JUNCTIONS;

HEAT TREATMENT;

EID: 84983097377     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTP.2001.1013744     Document Type: Conference Paper

References (4)

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2. L. Pelaz, G.H. Gilmer, V.C. Venizia, H.-J.Gossman, M. Jaraiz, and J. Barbolla, Appl. Phys. Lett. 74, 2017 (1999).
3. D. Lawther, U. Myler, P. Simpson, P Rousseau, P. Griffin and J. Plummer, Appl. Phys. Lett. 67, 3575 (1995)
4. P. Rousseau, P. Griffin, S. Kuehne and J. Plummer, Trans. On Electron Devices, Vol. 43, No. 4, April 1996, p. 547.