193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing

19th IEEE Symposium on Low-Power and High-Speed Chips, IEEE COOL Chips 2016 - Proceedings

Volumn , Issue , 2016, Pages

  Rossi, Davide ^a   Pullini, Antonio ^b   Loi, Igor ^a   Gautschi, Michael ^b   Gurkaynak, Frank Kagan ^b   Teman, Adam ^c,d   Constantin, Jeremy ^c   Burg, Andreas ^c   Miro Panades, Ivan ^e   Beign, Edith ^e   Clermidy, Fabien ^e   Abouzeid, Fady ^f   Flatresse, Philippe ^f   Benini, Luca ^a,b  

^a UNIVERSITY OF BOLOGNA   (Italy)

^b ETH ZURICH   (Switzerland)

^c EPFL   (Switzerland)

^d BAR ILAN UNIVERSITY   (Israel)

^e CEA LETI   (France)

^f STMICROELECTRONICS   (France)

Author keywords

Body Biasing; Energy Efficiency; Parallel Processing; Power Management; UTBB FD SOI

Indexed keywords

CLUSTER COMPUTING; FINITE DIFFERENCE METHOD; POWER MANAGEMENT; SIGNAL PROCESSING;

BODY BIASING; COMPUTING CLUSTERS; HIGH ENERGY EFFICIENCY; PARALLEL PROCESSING; PARALLEL WORKLOADS; SEQUENTIAL EXECUTION; UTBB FD-SOI; WEARABLE APPLICATIONS;

ENERGY EFFICIENCY;

EID: 84982806179     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CoolChips.2016.7503670     Document Type: Conference Paper

References (6)

1. A. Teman, et al., " Power, Area, and Performance Optimization of Standard Cell Memory Arrays through Controlled Placement " , ACM TOADES, 2016.
2. Jain, S., et al., " A 280mV-To-1.2V wide-operating-range IA-32 processor in 32nm CMOS, " ISSCC, 2012.
3. M. Saint-Laurent, et al., " A 28nm DSP Powered by an On-Chip LDO for High-Performance and Energy-Efficient Mobile Applications, " ISSCC, 2014.
4. R. Wilson, et al., " A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, Embedding FMAX Tracking, " ISSCC, 2014.
5. D. Rossi, et. al., " A 60 GOPS/W,-1.8V to 0.9V Body Bias ULP Cluster in 28nm UTBB FD-SOI technology " , Elsevier Journal of Solid State Electronics, 2015.
6. I. Miro-Panades, et.al., " A Fine-Grain Variation-Aware Dynamic Vdd-Hopping AVFS Architecture on a 32 nm GALS MPSoC, " IEEE Journal of Solid-State Circuits, Jul. 2014.