A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding F MAX tracking

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 57, Issue , 2014, Pages 452-453

  Wilson, Robin ^a   Beigne, Edith ^b   Flatresse, Philippe ^a   Valentian, Alexandre ^b   Abouzeid, Fady ^a   Benoist, Thomas ^b   Bernard, Christian ^b   Bernard, Sebastien ^b   Billoint, Olivier ^b   Clerc, Sylvain ^a   Giraud, Bastien ^b   Grover, Anuj ^a   Le Coz, Julien ^a   Panades, Ivan Miro ^b   Noel, Jean Philippe ^a   Pelloux Prayer, Bertrand ^a   Roche, Philippe ^a   Thomas, Olivier ^b   Thonnart, Y ^b   Turgis, David ^a   Clermidy, Fabien ^b   Magarshack, Philippe ^a   more..

^a STMICROELECTRONICS   (France)

^b CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY EFFICIENCY; SIGNAL PROCESSING;

COMPLEX ARITHMETIC; HIGH ENERGY EFFICIENCY; MAXIMUM FREQUENCY; MOBILE APPLICATIONS; OPERATING FREQUENCY; PERFORMANCE SPECIFICATIONS; PROCESSING COMPLEXITY; SERIAL INTERFACES;

VERY LONG INSTRUCTION WORD ARCHITECTURE;

EID: 84898069458     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2014.6757509     Document Type: Conference Paper

References (5)

1. D. Jacquet, et al., "2.6 GHZ Ultra Wide Voltage Range Energy Efficient Dual A9 in 28 nm UTBB FD-SOI," IEEE Symp. VLSI Circuits, pp. C44-C45, 2013.
2. G. Gammie, et al., "A 28nm 0.6V Low-Power DSP for Mobile Applications", ISSCC Dig. Tech. Papers, pp. 131-134, 2011.
3. S. Jain, et al., "A 280mV-to-1.2V Wide-Operating-Range IA-32 Processor in 32nm CMOS," ISSCC Dig. Tech. Papers, pp. 66-68, 2012.
4. S. Hsu, et al., "A 280mV-to-1.1V 256b Reconfigurable SIMD Vector Permutation Engine with 2-Dimensional Shuffle in 22nm CMOS", ISSCC Dig. Tech. Papers, pp. 178-180, 2012.
5. F. Abouzeid, et al., "A 45nm CMOS 0.35v-Optimized Standard Cell library for Ultra-Low Power Applications", IEEE International Symp. Low-Power Electronics and Design, pp. 225-230, 2009.