-
1
-
-
85077963574
-
Onyx: A protoype phase change memory storage array
-
Berkeley, CA, USA, HotStorage’11, USENIX Association
-
AKEL, A., CAULFIELD, A. M., MOLLOV, T. I., GUPTA, R. K., AND SWANSON, S. Onyx: a protoype phase change memory storage array. In Proceedings of the 3rd USENIX conference on Hot topics in storage and file systems (Berkeley, CA, USA, 2011), HotStorage’11, USENIX Association, pp. 2–2.
-
(2011)
Proceedings of the 3rd USENIX Conference on Hot Topics in Storage and File Systems
, pp. 2
-
-
Akel, A.1
Caulfield, A.M.2
Mollov, T.I.3
Gupta, R.K.4
Swanson, S.5
-
2
-
-
17644422802
-
Toward a universal memory
-
AKERMAN, J. Toward a universal memory. Science 308, 5721 (2005), 508–510.
-
(2005)
Science
, vol.308
, Issue.5721
, pp. 508-510
-
-
Akerman, J.1
-
3
-
-
84896342378
-
Path Processing using Solid State Storage
-
ATHANASSOULIS, M., BHATTACHARJEE, B., CANIM, M., AND ROSS, K. A. Path Processing using Solid State Storage. In Proceedings of the 3rd International Workshop on Accelerating Data Management Systems Using Modern Processor and Storage Architectures (ADMS 2012) (2012).
-
(2012)
Proceedings of the 3rd International Workshop on Accelerating Data Management Systems Using Modern Processor and Storage Architectures (ADMS 2012)
-
-
Athanassoulis, M.1
Bhattacharjee, B.2
Canim, M.3
Ross, K.A.4
-
4
-
-
4544337857
-
An 8mb demonstrator for high-density 1.8v phase-change memories
-
BEDESCHI, F., RESTA, C., ET AL. An 8mb demonstrator for high-density 1.8v phase-change memories. In VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on (2004), pp. 442–445.
-
(2004)
VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on
, pp. 442-445
-
-
Bedeschi, F.1
Resta, C.2
-
5
-
-
84866172223
-
Mercury: Host-side flash caching for the data center
-
BYAN, S., LENTINI, J., MADAN, A., PABON, L., CONDICT, M., KIMMEL, J., KLEIMAN, S., SMALL, C., AND STORER, M. Mercury: Host-side flash caching for the data center. In Mass Storage Systems and Technologies (MSST), 2012 IEEE 28th Symposium on (2012), pp. 1–12.
-
(2012)
Mass Storage Systems and Technologies (MSST), 2012 IEEE 28th Symposium on
, pp. 1-12
-
-
Byan, S.1
Lentini, J.2
Madan, A.3
Pabon, L.4
Condict, M.5
Kimmel, J.6
Kleiman, S.7
Small, C.8
Storer, M.9
-
12
-
-
85077206156
-
Flash caching on the storage client
-
USENIXATC’13, USENIX Association
-
HOLLAND, D. A., ANGELINO, E., WALD, G., AND SELTZER, M. I. Flash caching on the storage client. In Proceedings of the 11th USENIX conference on USENIX annual technical conference (2013), USENIXATC’13, USENIX Association.
-
(2013)
Proceedings of the 11th USENIX Conference on USENIX Annual Technical Conference
-
-
Holland, D.A.1
Angelino, E.2
Wald, G.3
Seltzer, M.I.4
-
13
-
-
39749201908
-
A 64mb chain feram with quad-bl architecture and 200mb/s burst mode
-
HOYA, K., TAKASHIMA, D., ET AL. A 64mb chain feram with quad-bl architecture and 200mb/s burst mode. In Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International (2006), pp. 459–466.
-
(2006)
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
, pp. 459-466
-
-
Hoya, K.1
Takashima, D.2
-
18
-
-
84863548648
-
Hybrid dram/pram-based main memory for single-chip cpu/GPU
-
KIM, D., LEE, S., CHUNG, J., KIM, D. H., WOO, D. H., YOO, S., AND LEE, S. Hybrid dram/pram-based main memory for single-chip cpu/gpu. In Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE (2012), pp. 888–896.
-
(2012)
Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE
, pp. 888-896
-
-
Kim, D.1
Lee, S.2
Chung, J.3
Kim, D.H.4
Woo, D.H.5
Yoo, S.6
Lee, S.7
-
19
-
-
70349254286
-
A pram and NAND flash hybrid architecture for high-performance embedded storage subsystems
-
New York, NY, USA, EMSOFT’08, ACM
-
KIM, J. K., LEE, H. G., CHOI, S., AND BAHNG, K. I. A pram and nand flash hybrid architecture for high-performance embedded storage subsystems. In Proceedings of the 8th ACM international conference on Embedded software (New York, NY, USA, 2008), EMSOFT’08, ACM, pp. 31–40.
-
(2008)
Proceedings of the 8th ACM International Conference on Embedded Software
, pp. 31-40
-
-
Kim, J.K.1
Lee, H.G.2
Choi, S.3
Bahng, K.I.4
-
20
-
-
85109877451
-
Write policies for host-side flash caches
-
FAST’13, USENIX Association
-
KOLLER, R., MARMOL, L., SUNDARARAMAN, S., TALAGALA, N., AND ZHAO, M. Write policies for host-side flash caches. In Proceedings of the 11th USENIX conference on File and Storage Technologies (2013), FAST’13, USENIX Association.
-
(2013)
Proceedings of the 11th USENIX Conference on File and Storage Technologies
-
-
Koller, R.1
Marmol, L.2
Sundararaman, S.3
Talagala, N.4
Zhao, M.5
-
21
-
-
70450235471
-
Architecting phase change memory as a scalable dram alternative
-
New York, NY, USA, ISCA’09, ACM
-
LEE, B. C., IPEK, E., MUTLU, O., AND BURGER, D. Architecting phase change memory as a scalable dram alternative. In Proceedings of the 36th annual international symposium on Computer architecture (New York, NY, USA, 2009), ISCA’09, ACM, pp. 2–13.
-
(2009)
Proceedings of the 36th Annual International Symposium on Computer Architecture
, pp. 2-13
-
-
Lee, B.C.1
Ipek, E.2
Mutlu, O.3
Burger, D.4
-
23
-
-
85092664155
-
Operating system support for nvm+dram hybrid main memory
-
Berkeley, CA, USA, HotOS’09, USENIX Association
-
MOGUL, J. C., ARGOLLO, E., SHAH, M., AND FARABOSCHI, P. Operating system support for nvm+dram hybrid main memory. In Proceedings of the 12th conference on Hot topics in operating systems (Berkeley, CA, USA, 2009), HotOS’09, USENIX Association, pp. 14–14.
-
(2009)
Proceedings of the 12th Conference on Hot Topics in Operating Systems
, pp. 14
-
-
Mogul, J.C.1
Argollo, E.2
Shah, M.3
Faraboschi, P.4
-
25
-
-
85080615915
-
-
PU R ESTO R AG E. FlashArray
-
PU R ESTO R AG E. FlashArray, Meet the new 3rd-generation FlashArray. http://www.purestorage.com/ flash- array/.
-
Meet the New 3rd-Generation FlashArray
-
-
-
26
-
-
84864832526
-
Preset: Improving performance of phase change memories by exploiting asymmetry in write times
-
Washington, DC, USA, ISCA’12, IEEE Computer Society
-
QURESHI, M. K., FRANCESCHINI, M. M., JAGMOHAN, A., AND LASTRAS, L. A. Preset: improving performance of phase change memories by exploiting asymmetry in write times. In Proceedings of the 39th Annual International Symposium on Computer Architecture (Washington, DC, USA, 2012), ISCA’12, IEEE Computer Society, pp. 380–391.
-
(2012)
Proceedings of the 39th Annual International Symposium on Computer Architecture
, pp. 380-391
-
-
Qureshi, M.K.1
Franceschini, M.M.2
Jagmohan, A.3
Lastras, L.A.4
-
27
-
-
70450273507
-
Scalable high performance main memory system using phase-change memory technology
-
New York, NY, USA, ISCA’09, ACM
-
QURESHI, M. K., SRINIVASAN, V., AND RIVERS, J. A. Scalable high performance main memory system using phase-change memory technology. In Proceedings of the 36th annual international symposium on Computer architecture (New York, NY, USA, 2009), ISCA’09, ACM, pp. 24–33.
-
(2009)
Proceedings of the 36th Annual International Symposium on Computer Architecture
, pp. 24-33
-
-
Qureshi, M.K.1
Srinivasan, V.2
Rivers, J.A.3
-
28
-
-
55449106208
-
Phase-change random access memory: A scalable technology
-
RAOUX, S., BURR, G., BREITWISCH, M., RETTNER, C., CHEN, Y., SHELBY, R., SALINGA, M., KREBS, D., CHEN, S.H., LUNG, H. L., AND LAM, C. Phase-change random access memory: A scalable technology. IBM Journal of Research and Development 52, 4.5 (2008), 465–479.
-
(2008)
IBM Journal of Research and Development
, vol.52
, Issue.45
, pp. 465-479
-
-
Raoux, S.1
Burr, G.2
Breitwisch, M.3
Rettner, C.4
Chen, Y.5
Shelby, R.6
Salinga, M.7
Krebs, D.8
Chen, S.H.9
Lung, H.L.10
Lam, C.11
|