Constraint graph analysis of multithreaded programs

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn 2003-January, Issue , 2003, Pages 4-14

  Cain, H W ^a   Lipasti, M H ^b   Nair, Ravi ^c  

^a University of Wisconsin Madison   (United States)

^b University of Wisconsin Madison   (United States)

^c IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MEMORY ARCHITECTURE; MULTITASKING; PARALLEL ARCHITECTURES;

COHERENCE MISS; CONSTRAINT GRAPH; FULL SYSTEM SIMULATORS; INSTRUCTION LEVEL PARALLELISM; MEMORY CONSISTENCY; MEMORY CONSISTENCY MODELS; MULTI-THREADED PROGRAMS; SCIENTIFIC WORKLOADS;

CACHE MEMORY;

EID: 84968877182     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2003.1237997     Document Type: Conference Paper

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