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Volumn , Issue , 2002, Pages 338-343

Predicting optimal process conditions for flip-chip assembly using copper column bumped dies

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; COPPER; ELECTRONICS PACKAGING; STRAIN ENERGY;

EID: 84964675026     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2002.1185694     Document Type: Conference Paper
Times cited : (13)

References (11)
  • 4
    • 0034832837 scopus 로고    scopus 로고
    • Predicting Solder Joint Reliability for Thermal, Power, & Bend Cycle within 25% Accuracy
    • st ECTC, 2001, pp. 255-264
    • (2001) st ECTC , pp. 255-264
    • Syed, A.1
  • 6
    • 0000112719 scopus 로고    scopus 로고
    • Reliability Analysis of Flip Chip Designs Via Computer Simulation
    • Lu, H., Bailey, C. and Cross, M., "Reliability Analysis of Flip Chip Designs Via Computer Simulation", J. of Electronic Packaging, vol. 122, 2000, pp. 214-219.
    • (2000) J. of Electronic Packaging , vol.122 , pp. 214-219
    • Lu, H.1    Bailey, C.2    Cross, M.3
  • 8
    • 84964604273 scopus 로고    scopus 로고
    • London
    • PHYSICA, Multi-Physics Ltd, London, http://www.multi-physics.com
    • Physica


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.