Low temperature activation of ion implanted dopants: A review

Extended Abstracts of the 3rd International Workshop on Junction Technology, IWJT 2002

Volumn , Issue , 2002, Pages 85-88

  Borland, J O ^a  

^a Varian Semiconductor Equip Assoc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84963594677     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWJT.2002.1225211     Document Type: Conference Paper

References (9)

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4. 2 or Si+B", J. Appl. Phys., vol. 50, no. 1, p. 183, 1979.
5. S. Onishi, K. Tanaka and K. Sakiyama, "A New Method for Evaluating Temperature Distribution by Using Si+B Implantation", SPIE, vol. 1189, Rapid Isothermal Processing, p. 83, 1989.
6. J. Borland and C. Galewski, "Using Dopant Activation of Implanted Wafers for Low Temperature (400°C-600"C) Measurement in CVD Equipment Design", 1998 International Conference on Ion Implantation Technology Proceedings, Kyoto, Japan, June 1998, p.1211.
7. 12 Icosahedron as a Double Acceptor", Jpn. J. Appl. Phys., vol. 33, no. 1B, p. 404, Jan. 1994.
8. 2 Sources", Proceedings of the Eleventh International Conference on Ion Implantation Technology, Austin, TX, June 1996, p. 607.
9. K. Tsuji, T. Takeuchi and T. Mogami, "High Performance 50-nm Physical Gate Length pMOSFETs by using Low Temperature Activation by Re-Crystallization Scheme", 1999 Symposium on VLSI Technology, section 2-1, p.9, Kyoto, Japan, June 1999.