A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 58, Issue , 2015, Pages 82-83

  Kulkarni, Jaydeep P ^a   Tokunaga, Carlos ^a   Aseron, Paolo ^a   Nguyen, Trang ^a   Augustine, Charles ^a   Tschanz, James ^a   De, Vivek ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY EFFICIENCY; TIMING CIRCUITS;

ACHIEVABLE PERFORMANCE; BUILDING BLOCKES; CRITICAL PATHS; DATA ACCESS PATTERNS; HIGH-PERFORMANCE MICROPROCESSORS; NORMAL OPERATIONS; OPERATING VOLTAGE; WITHIN-DIE VARIATIONS;

CMOS INTEGRATED CIRCUITS;

EID: 84940786289     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2015.7062936     Document Type: Conference Paper

References (5)

1. D. Ernst, et al., "Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation," IEEE/ACM MICRO, pp. 7-18, 2003.
2. K. A. Bowman, et al., "A 45nm Resilient Microprocessor Core for Dynamic Variation Tolerance," IEEE J. Solid-State Circuits, vol. 46, no. 1, pp. 194-204, 2011.
3. J. Tschanz, et al., "Tunable Replica Circuits and Adaptive Voltage-Frequency Techniques for Dynamic Voltage, Temperature, and Aging Variation Tolerance," IEEE Symp. on VLSI circuits, pp. 112-113, 2009.
4. C.-H. Jan, et. al., "A 22nm SoC Platform Technology Featuring 3-D Tri-Gate and High-k/Metal Gate, Optimized for Ultra-Low Power, High Performance and High Density SoC Applications," IEDM Dig. Tech. Papers, pp. 4-7, 2012.
5. N. Kurd, et al., "Haswell: A Family of IA 22nm Processors, ISSCC Dig. Tech. Papers, pp. 112-113, Feb. 2014.