A low power pseudo-random BIST technique

Proceedings of the 8th IEEE International On-Line Testing Workshop, IOLTW 2002

Volumn , Issue , 2002, Pages 140-144

  Basturkmen, N Z ^a   Reddy, S M ^a   Pomeranz, I ^b  

^a UNIVERSITY OF IOWA   (United States)

^b PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; CHAINS; ELECTRIC POWER UTILIZATION; INTEGRATED CIRCUIT TESTING; RECONFIGURABLE HARDWARE;

BENCHMARK CIRCUIT; BIST TECHNIQUES; CIRCUIT UNDER TEST; LOW POWER; PSEUDO RANDOM; SCAN CHAIN; SCAN DESIGNS; SWITCHING ACTIVITIES;

SWITCHING;

EID: 84962652932     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/OLT.2002.1030197     Document Type: Conference Paper

References (13)

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