Quality-aware data allocation in approximate DRAM?

2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2015

Volumn , Issue , 2015, Pages 89-98

  Raha, Arnab ^a   Jayakumar, Hrishikesh ^a   Sutar, Soubhagya ^a   Raghunathan, Vijay ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

Approximate Computing; DRAM Power Management; Intrinsic Application Resilience; Low Power Design

Indexed keywords

BINS; DYNAMIC RANDOM ACCESS STORAGE; ECONOMIC AND SOCIAL EFFECTS; ELECTRIC POWER SUPPLIES TO APPARATUS; EMBEDDED SYSTEMS; ENERGY CONSERVATION; ERRORS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MEMORY ARCHITECTURE; PROGRAM COMPILERS;

APPROXIMATE COMPUTING; DATA ALLOCATION; DESIGN PARADIGM; ERROR-RESILIENT; EXPERIMENTAL CHARACTERIZATION; INTRINSIC APPLICATION RESILIENCE; LOW-POWER DESIGN; NOVEL STRATEGIES;

INTEGRATED CIRCUIT DESIGN;

EID: 84962297091     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CASES.2015.7324549     Document Type: Conference Paper

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