Exploiting Partially-Forgetful Memories for Approximate Computing

IEEE Embedded Systems Letters

Volumn 7, Issue 1, 2015, Pages 19-22

  Shoushtari, Majid ^a   BanaiyanMofrad, Abbas ^a   Dutt, Nikil ^a  

^a Irvine   (United States)

Author keywords

Approximate computing; memory hierarchy; process variation; reliability

Indexed keywords

EMBEDDED SYSTEMS; ENERGY UTILIZATION; MEMORY ARCHITECTURE; RELIABILITY;

APPROXIMATE COMPUTING; ENERGY OVERHEADS; GUARD BANDS; LEAKAGE ENERGIES; MANUFACTURING VARIATION; MEMORY HIERARCHY; MEMORY SUBSYSTEMS; PROCESS VARIATION;

STATIC RANDOM ACCESS STORAGE;

EID: 84924333914     PISSN: 19430663     EISSN: None     Source Type: Journal    
DOI: 10.1109/LES.2015.2393860     Document Type: Article

References (19)

1. ITRS [Online]. Available: http://www.itrs.net, 2013
2. J. Wang and B. H. Calhoun, "Standby supply voltage minimization for reliable nanoscale SRAMs," presented at the Solid State Circ. Tech., 2004, InTech.
3. J. Liu et al., "RAIDR: Retention-aware intelligent DRAM refresh," presented at the ISCA, 2012.
4. W. Zhang and T. Li, "Characterizing and mitigating the impact of process variations on phase change ased memory systems," presented at the MICRO, 2009.
5. A. Sampson et al., "EnerJ: Approximate data types for safe and general low-power computation," presented at the PLDI, 2011.
6. L. Leem et al., "ERSA: Error resilient system architecture for probabilistic applications," presented at the DATE, 2010.
7. M. de Kruijf et al., "Relax: An architectural framework for software recovery of hardware faults," presented at the ISCA, 2010.
8. V. K. Chippa et al., "Analysis and characterization of inherent application resilience for approximate computing," presented at the DAC, 2013.
9. S. Liu et al., "Flikker: Saving DRAM refresh-power through critical data partitioning," presented at the ASPLOS, 2011.
10. M. Carbin et al., "Verifying quantitative reliability for programs that execute on unreliable hardware," presented at the OOPSLA, 2013.
11. A. Sampson et al., "Approximate storage in solid-state memories," presented at the MICRO, 2013.
12. M. Shoushtari et al., Relaxing manufacturing guard-bands in memories for energy saving Center for Embedded Computer Systems, Univ. California, Irvine, CA, USA, Tech. Rep. CECS-TR-14-04, May 2014.
13. A. BanaiyanMofrad et al., "FFT-cache: A flexible fault-tolerant cache architecture for ultra low voltage operation," presented at the CASES, 2011.
14. N. Binkert et al., "The gem5 simulator," SIGARCH Comput. Arch. News, vol. 39, no. 2, 2011.
15. ARM, "Cortex-A5 Processor Manual," [Online]. Available: http://www.arm.com
16. ARM, "Cortex-R4 Processor Manual," [Online]. Available: http://www.arm.com
17. M. Gottscho et al., "Power/capacity scaling: Energy savings with simple fault-tolerant caches," presented at the DAC, 2014.
18. M. R. Guthaus et al., "MiBench: A free, commercially representative embedded benchmark suite," presented at the WWC, 2001.
19. C. Bienia et al., "The PARSEC benchmark suite: Characterization and architectural implications," presented at the PACT, 2008.