Software pipelining for coarse-grained reconfigurable instruction set processors

Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

Volumn , Issue , 2002, Pages 338-344

  Barat, F ^a   Jayapala, M ^a   Op De Beeck, P ^a   Deconinck, G ^a  

^a UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; DESIGN; PROGRAM COMPILERS; PROGRAM PROCESSORS; RECONFIGURABLE HARDWARE;

ASSIGNMENT ALGORITHMS; COARSE-GRAINED RECONFIGURABLE; INSTRUCTION GENERATIONS; INSTRUCTION SCHEDULING; INTERMEDIATE REGISTERS; RECONFIGURABLE FUNCTIONAL UNIT; RECONFIGURABLE PROCESSORS; RECONFIGURABLE RESOURCES;

EMBEDDED SYSTEMS;

EID: 84962277619     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2002.994945     Document Type: Conference Paper

References (9)

1. M.F. Jacome and G. de Veciana, "Design Challenges for New Application-Specific Processors" IEEE Design & Test Computers, Vol. 17, No. 2, april 2000, pp. 40-50.
2. F. Barat and R. Lauwereins, "Reconfigurable Instruction Set Processors: A survey", Proceedings. 11th International Workshop on Rapid System Prototyping, 2000.
3. André DeHon, "The Density Advantage of Configurable Computing", IEEE Computer, Vol.33, No. 4, April 2000
4. C. Alippi, W. Fornaciari, L. Pozzi and M. Sami, "A DAG-Based Design Approach for Reconfigurable VLIW Processors", Proc. Of the IEEE Design and Test Conference in Europe, Munich, March 1999.
5. T.J. Callahan and J. Wawrzynek, "Instruction Level Parallelism for Reconfigurable Computing", Field-Programmable Logic and Applications, 8th International Workshop, September 1998.
6. M. Budiu and S. Goldstein. "Fast com pilation for pipelined reconfigurable fabrics", Proceedings of the 1999 ACM/SIGDA FPGA '99, Monterey, CA, Feb. 1999, pp. 195-205.
7. P. Op de Beeck, F. Barat, M. Jayapala, R. Lauwereins, "CRISP: A Template for Reconfigurable Instruction Set Architectures", Proceeding of Field Programmable Logic 2001.
8. Vicki H. Allan, Reese B. Jones, Randall M. Lee, and Stephen J. Allan ,"Software pipelining," ACM Computing Surveys, Vol. 27 No. 3, September 1995.
9. Rau, B.R., "Iterative Modulo Scheduling: An Algorithm For Software Pipelining Loops", MICRO-27. Proceedings of the 27th Annual International Symposium on Microarchitecture, 1994. Page(s): 63-74