Optimizing p-type ultra-shallow junctions for the 65 nm CMOS technology node

Proceedings of the International Conference on Ion Implantation Technology

Volumn 22-27-September-2002, Issue , 2002, Pages 21-24

  Pawlak, B J ^a   Lindsay, R ^b   Surdeanu, R ^a   Stolk, P ^a   Maex, K ^b   Pages, X ^c  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

^b IMEC   (Belgium)

^c ASM International NV   (Netherlands)

Author keywords

F coimplantation; Ge pre amorphization; spike anneal; ultra shallow junctions

Indexed keywords

AMORPHIZATION; CMOS INTEGRATED CIRCUITS; ECONOMIC AND SOCIAL EFFECTS; ION IMPLANTATION;

65 NM CMOS TECHNOLOGIES; CO-IMPLANT; CO-IMPLANTATION; JUNCTION ABRUPTNESS; JUNCTION DEPTH; PRE-AMORPHIZATION; SPIKE ANNEAL; ULTRA SHALLOW JUNCTION;

GERMANIUM;

EID: 84961385346     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IIT.2002.1257928     Document Type: Conference Paper

References (10)

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