A systolic array architecture for fast decoding of one-point AG codes and scheduling of parallel processing on it

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1719, Issue , 1999, Pages 302-313

  Sakata, Shojiro ^a   Kurihara, Masazumi ^a  

^a UNIVERSITY OF ELECTRO COMMUNICATIONS   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGEBRA; ALGORITHMS; CODES (SYMBOLS); COMPUTER ARCHITECTURE; DECODING; MEMORY ARCHITECTURE; PARALLEL ARCHITECTURES; SCHEDULING;

FAST DECODING ALGORITHMS; LINEAR TIME COMPLEXITY; LOCAL COMMUNICATIONS; ONE-POINT AG CODES; PARALLEL PROCESSING; PROCESSING UNITS; SYSTOLIC ARRAY ARCHITECTURE; TRANSMISSION DELAYS;

SYSTOLIC ARRAYS;

EID: 84957709923     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-46796-3_30     Document Type: Conference Paper

References (12)

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