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Volumn , Issue , 1997, Pages 378-
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A systolic array architecture for implementing a fast parallel decoding algorithm of one-point AG codes
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Author keywords
[No Author keywords available]
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Indexed keywords
COMPUTATIONAL COMPLEXITY;
COMPUTER ARCHITECTURE;
DECODING;
MATRIX ALGEBRA;
PARALLEL ALGORITHMS;
PARALLEL PROCESSING SYSTEMS;
POLYNOMIALS;
SYSTOLIC ARRAYS;
FAST PARALLEL DECODING ALGORITHM;
ONE POINT ALGEBRAIC GEOMETRY (AG) CODES;
BLOCK CODES;
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EID: 0030710268
PISSN: 21578095
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/ISIT.1997.613315 Document Type: Conference Paper |
Times cited : (4)
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References (7)
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