A fast parallel implementation of the Berlekamp-Massey algorithm with a 1D systolic array architecture

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 948, Issue , 1995, Pages 415-426

  Sakata, Shojiro ^a   Kurihara, Masazumi ^a  

^a UNIVERSITY OF ELECTRO COMMUNICATIONS   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGEBRA; CELLS; CYTOLOGY; MEMORY ARCHITECTURE; PARALLEL ARCHITECTURES;

BERLEKAMP-MASSEY ALGORITHM; EFFICIENT ARCHITECTURE; EXTENDED EUCLIDEAN ALGORITHM; LINEAR SYSTOLIC ARRAYS; LOCAL COMMUNICATIONS; MAXIMUM THROUGH-PUT; PARALLEL IMPLEMENTATIONS; SYSTOLIC ARRAY ARCHITECTURE;

SYSTOLIC ARRAYS;

EID: 84894354179     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: None     Document Type: Conference Paper

References (12)

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