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Volumn 2003-January, Issue , 2003, Pages 783-788

Current-driven wire planning for electromigration avoidance in analog circuits

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG CIRCUITS; COMPUTER AIDED DESIGN; DESIGN; ELECTROMIGRATION; RECONFIGURABLE HARDWARE; WIRE;

EID: 84954409674     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2003.1195125     Document Type: Conference Paper
Times cited : (41)

References (16)
  • 1
    • 84937650904 scopus 로고
    • Electromigration - A brief survey and some recent results
    • Dec
    • J. R. Black, "Electromigration - a brief survey and some recent results", Proc. IEEE Int. Reliability Physics Symposium, Dec. 1968, pp. 338-347.
    • (1968) Proc. IEEE Int. Reliability Physics Symposium , pp. 338-347
    • Black, J.R.1
  • 2
    • 0015142451 scopus 로고
    • Electromigration and failure in electronics: An introduction
    • F. M. D'Heurle, "Electromigration and failure in electronics: an introduction", Proc. of the IEEE, Vol. 59, no. 10, 1971, pp. 1409-1417.
    • (1971) Proc. of the IEEE , vol.59 , Issue.10 , pp. 1409-1417
    • D'Heurle, F.M.1
  • 3
    • 0028448170 scopus 로고
    • Failure mechanism models for electromigration
    • D. Young, A. Christou, "Failure mechanism models for electromigration", IEEE Trans. on Reliability, Vol. 43, no. 2, 1994, pp. 186-192.
    • (1994) IEEE Trans. on Reliability , vol.43 , Issue.2 , pp. 186-192
    • Young, D.1    Christou, A.2
  • 4
    • 0020098412 scopus 로고
    • Single layer routing of power and ground networks in integrated circuits
    • Z. A. Syed, A. Gamal, "Single layer routing of power and ground networks in integrated circuits", Journal of Digital Systems, vol. VI, no. 1, 1982, pp. 53-63.
    • (1982) Journal of Digital Systems , vol.6 , Issue.1 , pp. 53-63
    • Syed, Z.A.1    Gamal, A.2
  • 5
    • 0020834612 scopus 로고
    • Automatic variable-width routing for VLSI
    • Oct
    • H.-J. Rothermel, D. A. Mlynski, "Automatic variable-width routing for VLSI", IEEE TCAD, vol. CAD-2, no. 4, Oct. 1983, pp. 271-284.
    • (1983) IEEE TCAD , vol.CAD-2 , Issue.4 , pp. 271-284
    • Rothermel, H.-J.1    Mlynski, D.A.2
  • 6
    • 0020509141 scopus 로고
    • Laying the power and ground wires on a VLSI chip
    • A. S. Moulton, "Laying the power and ground wires on a VLSI chip", Proc. Design Automation Conf., 1983, pp. 754-755.
    • (1983) Proc. Design Automation Conf. , pp. 754-755
    • Moulton, A.S.1
  • 7
    • 0023545872 scopus 로고
    • A new area-efficient power routing algorithm for VLSI layout
    • S. Haruyama, D. Fussel, "A new area-efficient power routing algorithm for VLSI layout", Proc. ICCAD, 1987, pp. 38-41.
    • (1987) Proc. ICCAD , pp. 38-41
    • Haruyama, S.1    Fussel, D.2
  • 8
    • 0023269697 scopus 로고
    • An automated design of minimum-area IC power/ground nets
    • S. Chowdhury, "An automated design of minimum-area IC power/ground nets", Proc. Design Automation Conf., 1987, pp. 223-229.
    • (1987) Proc. Design Automation Conf. , pp. 223-229
    • Chowdhury, S.1
  • 10
    • 0032690819 scopus 로고    scopus 로고
    • A floorplan-based planning methodology for power and clock distribution in ASICs
    • J.-S. Yim, S.-O. Bae, Ch.-M. Kyung, "A floorplan-based planning methodology for power and clock distribution in ASICs", Proc. Design Automation Conf., 1999, pp. 766-771.
    • (1999) Proc. Design Automation Conf. , pp. 766-771
    • Yim, J.-S.1    Bae, S.-O.2    Kyung, Ch.-M.3
  • 11
    • 0032643254 scopus 로고    scopus 로고
    • Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings
    • X.-D. Tan, et.al., "Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings", Proc. Design Automation Conf., 1999, pp. 78-83.
    • (1999) Proc. Design Automation Conf. , pp. 78-83
    • Tan, X.-D.1
  • 12
    • 84893638973 scopus 로고    scopus 로고
    • Single step current driven routing of multiterminal signal nets for analog applications
    • T. Adler, E. Barke, "Single step current driven routing of multiterminal signal nets for analog applications", Proc. Design, Automation and Test in Europe (DATE), 2000, pp. 446-450.
    • (2000) Proc. Design, Automation and Test in Europe (DATE) , pp. 446-450
    • Adler, T.1    Barke, E.2
  • 13
    • 0033681636 scopus 로고    scopus 로고
    • A current driven routing and verification methodology for analog applications
    • T. Adler, et. al. "A current driven routing and verification methodology for analog applications", Proc. Design Automation Conf., 2000, pp. 385-389.
    • (2000) Proc. Design Automation Conf. , pp. 385-389
    • Adler, T.1
  • 14
    • 84962280173 scopus 로고    scopus 로고
    • Electromigration avoidance in analog circuits: Two methodologies for current-driven routing
    • J. Lienig, G. Jerke, T. Adler, "Electromigration avoidance in analog circuits: two methodologies for current-driven routing ", Proc. ASP-DAC/VLSI Design 2002, pp. 372-378.
    • Proc. ASP-DAC/VLSI Design 2002 , pp. 372-378
    • Lienig, J.1    Jerke, G.2    Adler, T.3
  • 16
    • 77951153495 scopus 로고    scopus 로고
    • Hierarchical current density verification for electromigration analysis in arbitrarily shaped metallization patterns of analog circuits
    • G. Jerke, J. Lienig, "Hierarchical current density verification for electromigration analysis in arbitrarily shaped metallization patterns of analog circuits", Proc. Design, Automation and Test in Europe (DATE), 2002, pp. 464-469.
    • (2002) Proc. Design, Automation and Test in Europe (DATE) , pp. 464-469
    • Jerke, G.1    Lienig, J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.