Architectural and compiler strategies for dynamic power management in the COPPER project

Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems

Volumn 2001-January, Issue , 2000, Pages 25-33

  Azevedo, A ^a   Cornea, R ^a   Issenin, I ^a   Gupta, R ^a   Dutt, N ^a   Nicolau, A ^a   Veidenbaum, A ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Reconfigurable architectures

Indexed keywords

APPLICATION PROGRAMS; COMPUTER ARCHITECTURE; ELECTRIC POWER UTILIZATION; EMBEDDED SYSTEMS; POWER MANAGEMENT; PROGRAM COMPILERS; RECONFIGURABLE ARCHITECTURES; VOLTAGE SCALING;

APPLICATION PERFORMANCE; CONTROLLED DYNAMICS; DYNAMIC ADAPTATIONS; DYNAMIC POWER MANAGEMENT; EMBEDDED SYSTEM APPLICATIONS; ENERGY-CONSTRAINED; PERFORMANCE CONSTRAINTS; POWER SCHEDULING;

MEMORY ARCHITECTURE;

EID: 84951121885     PISSN: 15373223     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWIA.2001.955194     Document Type: Conference Paper

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