Low power design for systems on a chip

Proceedings - 12th Annual IEEE International ASIC/SOC Conference

Volumn , Issue , 1999, Pages 422-

  Irwin, Mary Jane ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DESIGN; ELECTRIC POWER SUPPLIES TO APPARATUS; SYSTEM-ON-CHIP;

DESIGN TECHNIQUE; GATE LEVELS; LOW-POWER DESIGN; POWER-ANALYSIS TECHNIQUES; SYSTEM LEVEL DESIGN; SYSTEM-ON-A-CHIP DESIGNS;

INTEGRATED CIRCUIT DESIGN;

EID: 84951100025     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASIC.1999.806549     Document Type: Conference Paper

References (5)

1. Chandrakasan, A. and R. Brodersen, Low Power Digital CMOS Design, Kluwer, 1995
2. Pedram, M, Power minimization in IC design, ACM TODAES, l(l):3-56, Jan. 1996.
3. Rabaey, J. and M. Pedram, Eds., Low Power Design Methodologies, Kluwer, 1996.
4. Rabaey, J., System level power estimation and optimization - Challenges and Perspectives, Proc. of iSU'ED, pp, 158-160, 1997.
5. Ycap, G., Practical Low Power Digital VLSI Design, Kluwer, 1998.