Noise in radio frequency circuits: Analysis and design implications

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2001-January, Issue , 2001, Pages 469-476

  Mehrotra, Amit ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CALCULATIONS; DESIGN; INTEGRATED CIRCUIT MANUFACTURE; PHASE LOCKED LOOPS; RADIO WAVES; RANDOM PROCESSES; STOCHASTIC SYSTEMS;

CIRCUIT EQUATION; DESIGN IMPLICATIONS; DESIGN TECHNIQUE; NOISE ANALYSIS; PHASE-FEEDBACK SYSTEM; RADIO FREQUENCY CIRCUIT; RF CIRCUIT DESIGN; STOCHASTIC CALCULUS;

ELECTRIC NETWORK ANALYSIS;

EID: 84949985285     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2001.915273     Document Type: Conference Paper

References (40)

1. J. C. Rudell, J.-J. Ou, R. S. Narayanaswami, G. Chien, J. A. Weldon, L. Lin, K.-C. Tsai, L. Tee, K. Khoo, D. Au, T. Robinson, D. Gema, M. Otsuka, and P. R. Gray, "Recent developments in high integration multi-standard CMOS transceivers for personal communication systems," in Proceedings 1998 International Symposium on Low Power Electronics and Design, pp. 149-154, 1998.
2. J. C. Rudell, J.-J. Ou, T. B. Cho, G. Chien, F. Brianti, J. A. Weldon, and P. R. Gray, "A 1.9-GHz wide-band IF double conversion CMOS receiver for cordless telephone applications," IEEE Journal of Solid-State Circuits, Vol. 32, pp. 2071-2088, Dec. 1997.
3. A. Dunlop, A. Demir, P. Feldmann, S. Kapur, D. Long, R. Melville, and J. Roy Chowdhury, "Tools and methodology for RF IC design," in Proceedings 1998 Design Automation Conference, pp. 414-420, 1998.
4. A. Demir and J. Roychowdhury, "Estimaiting noise in RF systems," in IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, pp. 199-202, 1998.
5. J. S. Roychowdhury, P. Feldmann, and D. E. Long, "Cyclostationary noise analysis of large RF circuits with multi-tone excitations," IEEE Journal of Solid State Circuits, Vol. 33, pp. 324-36, Mar. 1998.
6. G. J. Coram and J. L. Wyatt Jr., "Nonlinear device noise models: Satisfying the thermodynamic requirements," IEEE Transactions on Electron Devices, Vol. 46, pp. 184-193, Jan. 1999.
7. T. J. Aprille, Jr. and T. N. Trick, "A computer algorithm to determine the steady state response of nonlinear oscillators," IEEE Transactions on Circuit Theory, Vol. CT19, pp. 354-360, July 1972.
8. T. J. Aprille, Jr. and T. N. Trick, "Steady-state analysis of nonlinear circuits with periodic inputs," Proceedings of the IEEE, Vol. 60, pp. 108-114, Jan. 1972.
9. R. Telichevesky, K. S. Kundert, and J. K. White, "Efficient steady-state analysis based on matrix-free Krylov-subspace methods," in Proceedings of the 32nd Design Automation Conference, pp. 480-484, June 1995.
10. R. J. Gilmore and M. B. Steer, "Nonlinear circuit analysis using the method of harmonic balance-a review of the art. I. Introductory concepts," International Journal of Microwave and Millimeter-Wave Computer-Aided Engineering, Vol. 1, pp. 22-37, Jan. 1991.
11. R. J. Gilmore and M. B. Steer, "Nonlinear circuit analysis using the method of harmonic balance-a review of the art. II. Advanced concepts," International Journal of Microwave and Millimeter-Wave Computer-Aided Engineering, vol 1, pp. 159-180, Apr. 1991.
12. C. D. Hull and R. G. Meyer, "A systematic approach to the analysis of noise in mixers," IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Vol. 40, pp. 909-919, Dec. 1993.
13. M. Okumura, H. Tanimoto, and T. Sugawara, "Noise analysis method for nonlinear circuits with two frequency excitations using the computer," Electronics and Communications in Japan Part 3, Vol. 74, No. 4, pp. 41-50, 1991.
14. V. Rizzoli, F. Mastri, and D. Masotti, "General noise analysis of nonlinear microwave circuits by the piecewise harmonic-balance techniques," IEEE Transactions on Microwave Theory and Techniques, Vol. 42, pp. 807-819, May 1994.
15. D. B. Leeson, "A simple model of feedback oscillator noise spectrum," Proceedings of the IEEE, Vol. 54, pp. 329-330, Feb. 1966.
16. E. Hafner, "The effect of noise in oscillators," Proceedings of the IEEE, Vol. 54, pp. 179-198, Feb. 1966.
17. B. Razavi, "A study of phase noise in CMOS oscillators," IEEE Journal of Solid State Circuits, Vol. 31, pp. 331-43, Mar. 1996.
18. A. Hajimiri and T. H. Lee, "A general theory of phase noise in electrical oscillators," IEEE Journal of Solid-State Circuits, Vol. 33, pp. 179-94, Feb. 1998.
19. A. Mehrotra, Simulation and Modelling Techniques for Noise in Radio Frequency Integrated Circuits. PhD thesis, University of California, Berkeley, 1999.'
20. A. Demir, A. Mehrotra, and J. Roychowdhury, "Phase noise in oscillators: a unifying theory and numerical methods for characterization," IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Vol. 47, pp. 655-674, May 2000.
21. A. H. Nayfeh and D. T. Mook, Nonlinear Oscillations. John Wiley & Sons, 1979.
22. P. Hagedorn, Nichtlineare Schwingungen. Oxford University Press, 1981.
23. A. Demir, A. Mehrotra, and J. Roychowdhury, "Phase noise in oscillators: a unifying theory and numerical methods for characterisation," in Proceedings 1998 Design Automation Conference, pp. 26-31, 1998.
24. A. Demir, "Oscillator phase noise analysis: MNA formulation and colored noise," in Internation Conference on Computer-Aided Design, Digest of Technical Papers, 1998.
25. A. Mehrotra, "Noise analysis of phase-locked loops," in 2000 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers, 2000.
26. B. K. Oksendal, Stochastic differential equations: an introduction with applications. Springer-Verlag, 1998.
27. C. W. Gardiner, Handbook of stochastic methods for physics, chemistry, and the natural sciences, Vol. 13 of Springer series in synergetics. Berlin, Heidelberg, New York, Tokyo: Springer-Verlag, second ed., 1983.
28. A. Mehrotra and A. Sangiovanni-Vincentelli, "Noise analysis of non autonomous radio frequency circuits," in 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers, pp. 55-60, 1999.
29. H.-G. Brachtendorf, G. Welsch, R. Laur, and A. Bunse-Gerstner, "Numerical steady state analysis of electronic circuits driven by multi-tone signals" Electrical Engineering, Vol. 79, pp. 103-112, 1996.
30. H.-G. Brachtendorf, G. Welsch, and R. Laur, "A novel time-frequency method for the simulation of the steady state of circuits driven by multi-tone signals," in Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, Vol. 3, pp. 1508-1511, 1997.
31. J. S. Roychowdhury, "Efficient methods for simulating highly nonlinear multirate circuits," in Proceedings of the 34th Design Automation Conference, pp. 269-274, 1997.
32. K. L. Fong, C. D. Hull, and R. G. Meyer, "A class AB monolithic mixer for 900-MHz applications," IEEE Journal of Solid-State Circuits, Vol. 32, pp. 1166-1172, Aug. 1997.
33. V. F. Kroupa and L. Sojdr, "Phase-lock loops of higher orders," in Second International Conference on Frequency Control and Synthesis, pp. 65-68, 1989.
34. B. Kim, T C. Weigandt, and P. R. Gray, "PLL/DLL system noise analysis for low jitter clock syndiesizer design," in Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, Vol. 4, pp. 31-34, 1994.
35. U. L. Rohde, Microwave and wireless synthesizers: theory and design. Wiley, 1997.
36. J. C. Nallatamby, M. Prigent, J. C. Sarkissian, R. Quere, and J. Obregon, "A new approach to nonlinear analysis of noise behavior of synchronized oscillators and analog-frequency dividers," IEEE Transactions on Microwave Theory and Techniques, Vol. 46, pp. 1168-1171, Aug. 1998.
37. L. Lin, L. Tee, and P. R. Gray, "A 1.4GHz differential low-noise CMOS frequency synthesizer using a wideband PLL architecture," in Digest of Technical Papers, IEEE International Solid-State Circuits Conference, pp. 204-205, 2000.
38. K. Lim, S. Choi, and B. Kim, "Optimal loop bandwidth design for low noise PLL applications," in Proceedings of the ASP-DAC '97. Asia and South Pacific Design Automation Conference 1997, pp. 425-428, 1997.
39. K. Lim, C.-H. Park, and B. Kim, "Low noise clock synthesizer design using optimal bandwidth," in Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, Vol. 1, pp. 163-166, 1998.
40. J. F. Parker and D. Ray, "A 1,6-GHz CMOS PLL with on-chip loop filter," IEEE Journal of Solid-State Circuits, Vol. 33, pp. 337-343, Mar. 1998.