A standard-cell self-timed multiplier for energy and area critical synchronous systems

Proceedings - 2001 Conference on Advanced Research in VLSI, ARVLSI 2001

Volumn , Issue , 2001, Pages 188-201

  Killpack, K C ^a   Mercer, E ^a   Meyers, C J ^a  

^a Department of Electrical and Computer Engineering   (United States)

Author keywords

Auditory system; Batteries; Cities and towns; Clocks; Costs; Delay; Filters; Routing; Scheduling; Timing

Indexed keywords

CLOCKS; COSTS; FILTERS (FOR FLUIDS); SCHEDULING; SOLAR CELLS;

AUDITORY SYSTEMS; CITIES AND TOWNS; DELAY; ROUTING; TIMING;

DESIGN;

EID: 2942687107     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ARVLSI.2001.915560     Document Type: Conference Paper

References (17)

1. A. J. Acosta, R. Jiménez, A. Barriga, M. J. Bellido, M. Valencia, and J. L. Huertas. Design and characterisation of a CMOS VLSI self-timed multiplier architecture based on a bit-level pipelined-array structure. IEE Proceedings, Circuits, Devices and Systems, 145(4):247-253, August 1998.
2. R. G. Burford, X. Fan, and N. W. Bergmann. An 180 MHz 16 bit multiplier using asynchronous logic design techniques. In Proc. IEEE Custom Integrated Circuits Conference, pages 215-218, 1994.
3. Jen-Shiun Chiang and Jun-Yao Liao. A novel asynchronous control unit and the application to a pipelined multiplier. In Proc. International Symposium on Circuits and Systems, volume 2, pages 169-172, June 1998.
4. C. H. Lau, D. Renshaw, and J. Mavor. A self-timed wavefront array multiplier. In Proc. International Symposium on Circuits and Systems, pages 138-141, 1989.
5. J. B. Lipsher and K. Maheswaran. A 4-bit asynchronous pipelined multiplier in the Xilinx 4000 series FPGA. Technical report, University of California, Davis, 1994.
6. O. Salomon and H. Klar. Self-timed fully pipelined multipliers. In S. Furber and M. Edwards, editors, Asynchronous Design Methodologies, volume A-28 of IFIP Transactions, pages 45-55. Elsevier Science Publishers, 1993.
7. Kenneth Y. Yun, Peter A. Beerel, Vida Vakilotojar, Ayoob E. Dooply, and Julio Arceo. The design and verification of a high-performance low-control-overhead asynchronous differential equation solver. In Proceedings of International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 140-153. IEEE Computer Society Press, April 1997.
8. A. D. Booth. A signed binary multiplication technique. Quarterly Journal of Mechanical Applied Mathmatics, 4(2), 1951.
9. V. Chandramouli, Erik Brunvand, and Kent F. Smith. Self-timed design in GaAs - case study of a high-speed, parallel multiplier. IEEE Transactions on VLSI Systems, 4(1):146-149, March 1996.
10. Jaco Haans, Kees van Berkel, Ad Peeters, and Frits Schalij. Asynchronous multipliers as combinational handshake circuits. In S. Furber and M. Edwards, editors, Asynchronous Design Methodologies, volume A-28 of IFIP Transactions, pages 149-163. Elsevier Science Publishers, 1993.
11. Christian D. Nielsen and Alain J. Martin. Design of a delay-insensitive multiply-accumulate unit. Integration, the VLSI journal, 15(3):291-311, October 1993.
12. J. Sparsø, C. D. Nielsen, L. S. Nielsen, and J. Staunstrup. Design of self-timed multipliers: A comparison. In S. Furber and M. Edwards, editors, Asynchronous Design Methodologies, volume A-28 of IFIP Transactions, pages 165-179. Elsevier Science Publishers, 1993.
13. David Kearney and Neil W. Bergmann. Bundled data asynchronous multipliers with data dependant computation times. In Proceedings of International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 186-197. IEEE Computer Society Press, April 1997.
14. Mark Santoro and Mark A. Horowitz. SPIM: A pipelined 64x64-bit iterative multiplier. IEEE Journal of Solid-State Circuits, 24(2):487-493, April 1989.
15. L. Dadda. Some schemes for parallel multipliers. Alta Frequency, 34(5):349-356, March 1965.
16. Chris J. Myers. Computer-Aided Synthesis and Verification of Gate-Level Timed Circuits. PhD thesis, Dept. of Elec. Eng., Stanford University, October 1995.
17. José A. Tierno and Alain J. Martin. Low-energy asynchronous memory design. In Proceedings of International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 176-185, November 1994.