StReAm: Object-oriented programming of stream architectures using PAM-Blox

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn 2000-January, Issue , 2000, Pages 309-310

  Mencer, Oskar ^a   Hübert, Heiko ^a   Morf, Martin ^a   Flynn, Michael J ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASSOCIATIVE STORAGE; CLOCKS; COMPUTERS; DATA FLOW ANALYSIS; ELECTRIC POWER UTILIZATION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MICROPROCESSOR CHIPS; OXIDE FILMS; POLYMETHYL METHACRYLATES; PROGRAM COMPILERS; THROUGHPUT;

CLOCK FREQUENCY; DOMAIN SPECIFIC; FULLY PIPELINED; GENERAL-PURPOSE MICROPROCESSORS; HIGH POWER CONSUMPTION; HIGH THROUGHPUT; MICRO ARCHITECTURES; STREAM ARCHITECTURE;

OBJECT ORIENTED PROGRAMMING;

EID: 84949774743     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPGA.2000.903431     Document Type: Conference Paper

References (7)

1. O. Mencer, M. Morf, M. J. Flynn, PAM-Blox: High Performance FPCA Design for Adaptive Computing, IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, CA, 1998. http://arithmetic.stanford.edu/PAM-Blox
2. R. Laufer, R. Reed Taylor, H. Schmit PCI-PipeRench and SWORDAPI: A System for Stream-based Reconfigurable Computing, IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, CA, 1999.
3. aBerkeley Brass Project, SCORE: Stream Computations Organized for Reconfigurable Execution Fast Module Mapping and Placement for Datapaths in FPGAs, http://www.cs.berkeley.edu/Research/Projects/brass/SCORE
4. S. Rixner, W. J. Dally, U. J. Kapasi, B. Khailany, A. Lopez-Lagunas, P. R. Mattson, J. D. Owens, A Bandwidth-Efficient Architecture for Media Processing, Proceedings of the 31st Annual International Symposium on Microarchitecture, Dallas, Texas, Nov. 1998.
5. C. Ebeling, D. C. Cronquist, P. Franklin, J. Secosky, S. G. Berg, Mapping Applications to the RaPiD Configurable Architecture, IEEE Symposium on Field-Programmable Custom Computing Machines, Napa Valley, CA, 1997.
6. E. Linzer, E. Feig, New Scaled DCT Algorithms for Fused Multiply/Add Architectures, International Conference on Acoustics, Speech, and Signal Processing, Proceedings ICASSP.91, Vols.1-5, pp. 2201-2204, 1991.
7. O. Mencer, L. Séméria, M. Morf, J. M. Delosme, Application of Reconfigurable CORDIC Architectures, The Journal of VLSI Signal Processing, Special Issue: VLSI on Custom Computing Technology, Kluwer, March 2000.