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Volumn 24, Issue 2, 2000, Pages 211-221

Application of reconfigurable CORDIC architectures

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL GEOMETRY; COMPUTER AIDED DESIGN; DIGITAL ARITHMETIC; DIGITAL COMPUTERS; FIELD PROGRAMMABLE GATE ARRAYS; VLSI CIRCUITS;

EID: 0342756795     PISSN: 09225773     EISSN: None     Source Type: Journal    
DOI: 10.1023/a:1008145506415     Document Type: Article
Times cited : (25)

References (23)
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    • CORDIC Algorithms in Four Dimensions, Advanced Signal Processing Algorithms, Architectures and Implementations
    • San Diego, CA, July
    • J.-M. Delosme and S.-F. Hsiao, "CORDIC Algorithms in Four Dimensions, Advanced Signal Processing Algorithms, Architectures and Implementations," Proc. SPIE 1348, San Diego, CA, July 1990, pp. 349-360.
    • (1990) Proc. SPIE 1348 , pp. 349-360
    • Delosme, J.-M.1    Hsiao, S.-F.2
  • 6
    • 84919346176 scopus 로고
    • The CORDIC Trigonometric Computing Technique
    • Sept.
    • J.E. Volder, "The CORDIC Trigonometric Computing Technique," IRE Trans. on Electronic Computers, vol. EC-8, no. 3, Sept. 1959, pp. 330-334.
    • (1959) IRE Trans. on Electronic Computers , vol.EC8 , Issue.3 , pp. 330-334
    • Volder, J.E.1
  • 7
    • 0001500758 scopus 로고
    • A Unified Algorithm for Elementary Functions
    • J.S. Walther, "A Unified Algorithm for Elementary Functions," AFIPS Conf, Proc., vol. 38, 1971, pp. 379-385.
    • (1971) AFIPS Conf, Proc. , vol.38 , pp. 379-385
    • Walther, J.S.1
  • 8
    • 0001527561 scopus 로고
    • Automatic Computation of Exponentials, Logarithms, Ratios and Square Roots
    • July
    • T.C. Chen, "Automatic Computation of Exponentials, Logarithms, Ratios and Square Roots," IBM Journal of Research and Development, July 1972.
    • (1972) IBM Journal of Research and Development
    • Chen, T.C.1
  • 10
    • 85013590781 scopus 로고
    • Generalized CORDIC for Digital Signal Processing
    • Paris, France, May See also Ph.D. Thesis, E.E. Dept., Stanford, Aug. 1980
    • D.T.L. Lee and M. Morf, "Generalized CORDIC for Digital Signal Processing," Proc. 1982 Int. Conf. on Acoustics, Speech and Signal Processing (ICASSP), Paris, France, May 1982, pp. 1748-1751. See also Ph.D. Thesis, E.E. Dept., Stanford, Aug. 1980.
    • (1982) Proc. 1982 Int. Conf. on Acoustics, Speech and Signal Processing (ICASSP) , pp. 1748-1751
    • Lee, D.T.L.1    Morf, M.2
  • 12
  • 14
    • 0032760882 scopus 로고    scopus 로고
    • Dynamic Circuit Generation for Boolean Satisfiability in an Object-Oriented Design Environment
    • Jan.
    • O. Mencer and M. Platzner, "Dynamic Circuit Generation for Boolean Satisfiability in an Object-Oriented Design Environment," Hawaii Int. Conf. on System Sciences (ConfigWare Track), Jan. 1999.
    • (1999) Hawaii Int. Conf. on System Sciences (ConfigWare Track)
    • Mencer, O.1    Platzner, M.2
  • 15
    • 0343487618 scopus 로고    scopus 로고
    • Synopsys FPGA Express
    • Synopsys FPGA Express, http://www.synopsys.com/products/ fpga_solution/fpga_express.html.
  • 17
    • 0343051778 scopus 로고    scopus 로고
    • Synopsys Products
    • Synopsys Products, http://www.synopsys.com/products.
  • 19
    • 0019715660 scopus 로고
    • A VLSI Speech Anaysis Chip Set Utilizing Co-ordinate Rotation Arithmetic
    • Chicago, Illinois, April
    • H.M. Ahmed, P.H. Ang, and M. Morf, "A VLSI Speech Anaysis Chip Set Utilizing Co-ordinate Rotation Arithmetic," Proc. 1981 Int. Symp. on Circuits and Systems (ISCAS), Chicago, Illinois, April 1981, pp. 737-741.
    • (1981) Proc. 1981 Int. Symp. on Circuits and Systems (ISCAS) , pp. 737-741
    • Ahmed, H.M.1    Ang, P.H.2    Morf, M.3
  • 21
    • 0019267415 scopus 로고
    • State-Space Structure of Ladder Canonical Forms
    • Dec.
    • M. Morf and D.T. Lee, "State-Space Structure of Ladder Canonical Forms," Proc. 18th Conf. on Control and Design, Dec. 1980, pp. 1221-1224.
    • (1980) Proc. 18th Conf. on Control and Design , pp. 1221-1224
    • Morf, M.1    Lee, D.T.2
  • 23
    • 84956862926 scopus 로고    scopus 로고
    • Instruction Level Parallelism for Reconfigurable Computing
    • Tallinn, Estonia, Sept. Publilshed in Springer-Verlag LNCS 1482
    • T.J. Callahan and J. Wawrzynek, "Instruction Level Parallelism for Reconfigurable Computing," FPL'98, Tallinn, Estonia, Sept. 1998, pp. 248-258. Publilshed in Springer-Verlag LNCS 1482.
    • (1998) FPL'98 , pp. 248-258
    • Callahan, T.J.1    Wawrzynek, J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.