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Volumn 14, Issue 4, 1995, Pages 413-422

A Simple Theorem Prover Based on Symbolic Trajectory Evaluation and BDD's

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPROXIMATION THEORY; AUTOMATION; BOOLEAN ALGEBRA; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SYSTEMS; DATA REDUCTION; FINITE AUTOMATA; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; VLSI CIRCUITS;

EID: 0029291994     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.372367     Document Type: Article
Times cited : (28)

References (19)
  • 1
    • 0027594398 scopus 로고
    • Formal verification of sequential hardware: A tutorial
    • May
    • M. C. McFarland, “Formal verification of sequential hardware: A tutorial,” IEEE Trans. Computer-Aided Design, vol. 12, no. 5, pp. 633–654, May 1993.
    • (1993) IEEE Trans. Computer-Aided Design , vol.12 , Issue.5 , pp. 633-654
    • McFarland, M.C.1
  • 3
    • 0020900726 scopus 로고
    • Automatic verification of finite-state concurrent systems using temporal logic specifications: A practical approach
    • New York ACM
    • E. M. Clarke, E. A. Emerson, and A. P. Sistla, “Automatic verification of finite-state concurrent systems using temporal logic specifications: A practical approach,” in Proc. 10th ACM Symp. Principles Programming Languages, New York, 1983, ACM, pp. 117–126.
    • (1983) Proc. 10th ACM Symp. Principles Programming Languages , pp. 117-126
    • Clarke, E.M.1    Emerson, E.A.2    Sistla, A.P.3
  • 4
    • 0011589477 scopus 로고
    • Verifying temporal properties of sequential machines without building their state diagram
    • June Lecture Notes in Computer Science 531
    • O. Coudert, J. C. Madre, and C. Berthet, “Verifying temporal properties of sequential machines without building their state diagram”, in CAV '90: Proc. 2nd Int. Workshop Computer-Aided Verification, June 1990, Lecture Notes in Computer Science 531.
    • (1990) CAV '90: Proc. 2nd Int. Workshop Computer-Aided Verification
    • Coudert, O.1    Madre, J.C.2    Berthet, C.3
  • 5
    • 0026913667 scopus 로고
    • Symbolic boolean manipulation with ordered binary-decision diagrams
    • Sept.
    • R. E. Bryant, “Symbolic boolean manipulation with ordered binary-decision diagrams,” ACM Computing Surveys, vol. 24, no. 3, pp. 293–318, Sept. 1992.
    • (1992) ACM Computing Surveys , vol.24 , Issue.3 , pp. 293-318
    • Bryant, R.E.1
  • 6
    • 35048900689 scopus 로고
    • Symbolic model checking: 1020 states and beyond
    • June
    • J. R. Burch, E. M. Clarke, and K. L. McMillan, “Symbolic model checking: 1020 states and beyond,” Inform. Computation, vol. 98, no. 2, pp. 142–170, June 1992.
    • (1992) Inform. Computation , vol.98 , Issue.2 , pp. 142-170
    • Burch, J.R.1    Clarke, E.M.2    McMillan, K.L.3
  • 7
    • 0026107125 scopus 로고
    • On the complexity of vlsi implementations and graph representations of boolean functions with application to integer multiplication
    • Feb.
    • R. E. Bryant, “On the complexity of vlsi implementations and graph representations of boolean functions with application to integer multiplication,” IEEE Trans. Comput., vol. 20, no. 2, pp. 205–213, Feb. 1991.
    • (1991) IEEE Trans. Comput. , vol.20 , Issue.2 , pp. 205-213
    • Bryant, R.E.1
  • 8
    • 0027189118 scopus 로고
    • Linking BDD-based symbolic evaluation to interactive theorem-proving
    • June
    • J. J. Joyce and C.-J. H. Seger, “Linking BDD-based symbolic evaluation to interactive theorem-proving,” in Proc. 30th Design Automation Conf. June 1993, pp. 469–474.
    • (1993) Proc. 30th Design Automation Conf. , pp. 469-474
    • Joyce, J.J.1    Seger, C.-J.H.2
  • 10
    • 84956986947 scopus 로고
    • Combining model checking and theorem proving to verify parallel processes
    • July
    • H. Hungar, “Combining model checking and theorem proving to verify parallel processes,” in Proc. 5th Int. Conf. on Computer-Aided Verification, July 1993, pp. 154-165.
    • (1993) Proc. 5th Int. Conf. on Computer-Aided Verification , pp. 154-165
    • Hungar, H.1
  • 12
    • 0001510331 scopus 로고
    • Formal verification by symbolic evaluation of partially-ordered trajectories
    • to be published in Mar.
    • C.-J. H. Seger and R. E. Bryant, “Formal verification by symbolic evaluation of partially-ordered trajectories,” to be published in J. Formal Methods in Syst. Design, vol. 6, pp. 147–189, Mar. 1995.
    • (1995) J. Formal Methods in Syst. Design , vol.6 , pp. 147-189
    • Seger, C.-J.H.1    Bryant, R.E.2
  • 13


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.