FPGA resource reduction through truncated multiplication

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2147, Issue , 2001, Pages 574-583

  Wires, Kent E ^a   Schulte, Michael J ^b   McCarley, Don ^a  

^a AGERE SYSTEMS   (United States)

^b LEHIGH UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER CIRCUITS;

BOOTH ENCODING; CORRECTION TERMS; PARALLEL MULTIPLIERS; PERFORMANCE ENHANCING; TOTAL ERRORS; TRUNCATED MULTIPLICATION; TRUNCATED MULTIPLIERS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 84949198048     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-44687-7_59     Document Type: Conference Paper

References (17)

1. S. Oberman, F. Weber, N. Juffa, and G. Favor, “AMD 3DNow! Technology and the K6-2 Microprocessor,” in Proceedings of Hot Chips 10, pp. 245–254, 1998.
2. S. Thakkur and T. Huff, “Internet Streaming SIMD Extensions,” Computer, vol. 32, no. 12, pp. 26–34, 1999.
3. AltiVec Technology Programming Environments Manual. Motorola, Inc., 1998.
4. K. Diefendorff, P. Dubey, R. Hochsprung, and H. Scale, “AltiVec Extension to PowerPC Accelerates Media Processing,” IEEE Micro, vol. 20, no. 2, pp. 85–95, 2000.
5. J. R. Boddie et al., “A 32-Bit Floating-Point DSP with C Compiler,” in Conference Record of the Twenty-Second Asilomar Conference on Signals, Systems and Computers, vol. 2, pp. 880–884, 1989.
6. N. Vasseghi, K. Yeager, E. Sarto, and M. Seddighnezhad, “A 200-MHz Superscalar RISC Microprocessor,” IEEE Journal of Solid-State Circuits, vol. 31, no. 11, pp. 1675–1686, 1996.
7. R. Weiss, “32-Bit Floating-Point DSP Processors,” EDN, vol. 36, no. 23, pp. 127–146, 1991.
8. M. Thornton, J. Gaiche, and J. Lemieux, “Tradeoff Analysis of Integer Multiplier Circuits Implemented in FPGAs,” in IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, pp. 301–304, 1999.
9. Lucent Technologies, “Implementing and Optimizing Multipliers in ORCA FPGAs,” Technical Application Note, 1997.
10. D. McCarley, S. Megeed, and J. Fried, “Module Generated Multipliers in Field Programmable Gate Arrays,” Lehigh University Technical Report, 1999.
11. A. V. Oppenheim and R. W. Schafer, Digital Signal Processing. Prentice-Hall, Inc., 1975.
12. M. J. Schulte and E. E. Swartzlander, Jr., “Truncated Multiplication with Correction Constant,” in VLSI Signal Processing, VI, pp. 388–396, 1993.
13. E. J. King and E. E. Swartzlander, Jr., “Data-Dependent Truncated Scheme for Parallel Multiplication,” in Proceedings of the Thirty First Asilomar Conference on Signals, Circuits and Systems, pp. 1178–1182, 1998.
14. M. J. Schulte, J. G. Jansen, and J. E. Stine., “Reduced Power Dissipation Through Truncated Multiplication,” in IEEE Alessandro Volta Memorial International Workshop on Low Power Design, pp. 61–69, 1999.
15. L. Dadda, “Some Schemes for Parallel Multipliers,” Alta Frequenza, vol. 34, pp. 349–356, 1965.
16. Lucent Technologies, “ORCA OR3LxxxB Series Field-Programmable Gate Arrays,” Product Brief, 1999.
17. Lucent Technologies, “ORCA OR3LxxxB Series Field-Programmable Gate Arrays,” Data Addendum, 1999.