An FPGA based parameterizable system for matrix product implementation

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

Volumn 2002-January, Issue , 2002, Pages 75-79

  Amira, A ^a   Bensaali, F ^a  

^a QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

Author keywords

Arithmetic; Array signal processing; Design methodology; Field programmable gate arrays; Filtering; Image coding; Image processing; Signal processing; Speech coding; Speech processing

Indexed keywords

CODES (SYMBOLS); DIGITAL ARITHMETIC; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FILTER BANKS; FILTRATION; IMAGE CODING; IMAGE PROCESSING; SPEECH CODING; SPEECH PROCESSING;

ARRAY SIGNAL PROCESSING; BAUGH-WOOLEY ALGORITHM; DESIGN METHODOLOGY; DISTRIBUTED ARITHMETIC; DISTRIBUTED ARITHMETIC DESIGN; EFFICIENT IMPLEMENTATION; MATRIX MULTIPLICATION; SIGNAL AND IMAGE PROCESSING;

SIGNAL PROCESSING;

EID: 84948953898     PISSN: 15206130     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SIPS.2002.1049688     Document Type: Conference Paper

References (12)

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