High throughput FPGA implementation of a Bit-level matrix product

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

Volumn , Issue , 2000, Pages 356-364

  Amira, A ^a   Bouridane, A ^a   Milligan, P ^a   Sage, P ^a  

^a QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; COMPUTATIONAL COMPLEXITY; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; MATHEMATICAL MODELS; MATRIX ALGEBRA; MULTIPLYING CIRCUITS; VECTORS;

BAUGH-WOOLEY ALGORITHM; MATRIX PRODUCT ALGORITHM;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0034514659     PISSN: 15206130     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)