Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product

Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Volumn 2002-January, Issue , 2002, Pages 75-79

  Lin, I Cheng ^a   Huang, Chih Yao ^a   Chao, Chuan Jane ^a   Ker, Ming Dou ^b   Chuan, Sung Yu ^a   Leu, Len Yi ^a   Chiu, Fu Chien ^a   Tseng, Jen Chou ^a  

^a WINBOND ELECTRONICS CORPORATION   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Breakdown voltage; Circuit testing; Clamps; CMOS integrated circuits; Electrostatic discharge; Pins; Power supplies; Protection; Resistors; Thyristors

Indexed keywords

CLAMPING DEVICES; CMOS INTEGRATED CIRCUITS; ELECTRIC BREAKDOWN; ELECTRIC NETWORK ANALYSIS; ELECTROSTATIC DEVICES; ELECTROSTATIC DISCHARGE; INTEGRATED CIRCUIT TESTING; INTEGRATED CIRCUITS; OUTAGES; RESISTORS; THYRISTORS;

CIRCUIT TESTING; ESD PROTECTION CIRCUIT; HIGH VOLTAGE CMOS; HIGH-VOLTAGE IC; ON-CHIP ESD PROTECTION; PINS; POWER SUPPLY; PROTECTION;

FAILURE ANALYSIS;

EID: 84948770314     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPFA.2002.1025615     Document Type: Conference Paper

References (4)

1. IC Latch-up Test, EIA/JEDEC Standard No. 78, Electronic Industries Association, 1997.
2. M. J. Hargrove, et al., "Latchup in CMOS technology," in Proc. of IEEE Int. Reliability Physics Symp., 1998, pp. 269-278.
3. M.-D. Ker, et al., "Compact layout rule extraction for latchup prevention in a 0.25-um shallow-trench-isolation silicided bulk CMOS process," in Proc. of Int. Symp. on Quality Electronic Design, 2001, pp. 267-272.
4. M.-D. Ker, "Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI," IEEE Trans. on Elec. Dev., No. 1, pp. 173-183, 1999.