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Volumn 3203, Issue , 2004, Pages 868-873

Mapping DSP applications to a high-performance reconfigurable coarse-grain data-path

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL SIGNAL PROCESSING; MAPPING;

EID: 84947917161     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-30117-2_91     Document Type: Conference Paper
Times cited : (3)

References (7)
  • 1
    • 84893641728 scopus 로고    scopus 로고
    • A Decade of Reconfigurable Computing: A Visionary Retrospective
    • Hartenstein, R.: A Decade of Reconfigurable Computing: A Visionary Retrospective. Proc. of Design and Test in Europe (DATE) (2001) 642-649
    • (2001) Proc. Of Design and Test in Europe (DATE) , pp. 642-649
    • Hartenstein, R.1
  • 2
    • 0030211562 scopus 로고    scopus 로고
    • Performance Optimization Using Template Mapping for Datapath- Intensive High-Level Synthesis
    • Corazao, M. R., et al.: Performance Optimization Using Template Mapping for Datapath- Intensive High-Level Synthesis. IEEE Trans. on Computer Aided Design, vol.15, no. 2 (1996) 877-888
    • (1996) IEEE Trans. On Computer Aided Design , vol.15 , Issue.2 , pp. 877-888
    • Corazao, M.R.1
  • 3
    • 0036826798 scopus 로고    scopus 로고
    • Instruction Generation for Hybrid Reconfigurable Systems
    • Kastner, R., et al.: Instruction Generation for Hybrid Reconfigurable Systems. ACM Trans. on Design Automation of Embedded Systems, vol. 7, no.4 (2002) 605-627
    • (2002) ACM Trans. On Design Automation of Embedded Systems , vol.7 , Issue.4 , pp. 605-627
    • Kastner, R.1
  • 4
    • 2442428419 scopus 로고    scopus 로고
    • Application-Specific Instruction Generation for Configurable Processor Architectures
    • Cong, J., et al.: Application-Specific Instruction Generation for Configurable Processor Architectures. Proc. of the ACM Int. Symposium on FPGA (2004) 183-189
    • (2004) Proc. Of the ACM Int. Symposium on FPGA , pp. 183-189
    • Cong, J.1
  • 6
    • 0022141776 scopus 로고
    • Fat-Trees: Universal Networks for Hardware Efficient Supercomputing
    • Leiserson, C.E.: Fat-Trees: Universal Networks for Hardware Efficient Supercomputing. IEEE Transactions on Computers, vol. 43, no. 10 (1985) 892-901
    • (1985) IEEE Transactions on Computers , vol.43 , Issue.10 , pp. 892-901
    • Leiserson, C.E.1
  • 7
    • 84947947322 scopus 로고    scopus 로고
    • Synopsys Design Compiler©: www.synopsys.com (2004)
    • (2004)


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.