System-level modeling of dynamically reconfigurable co-processors

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3203, Issue , 2004, Pages 881-885

  Qu, Yang ^a   Tiensyrjä, Kari ^a   Masselos, Kostas ^b  

^a VTT TECHNICAL RESEARCH CENTRE OF FINLAND   (Finland)

^b Intracom Holdings SA   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

COPROCESSOR; HIGH LEVEL SYNTHESIS;

ADAPTABLE SYSTEM; DESIGN ALTERNATIVES; DESIGN METHOD; ESTIMATION TOOLS; PERFORMANCE IMPACT; RECONFIGURABLE COPROCESSORS; SUPPORT SYSTEMS; SYSTEM-LEVEL MODELING;

INTEGRATED CIRCUIT DESIGN;

EID: 84947909770     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-30117-2_93     Document Type: Conference Paper

References (5)

1. Robinson, D., Lysaght, P.: Methods of exploiting simulation technology for simulating the timing of dynamically reconfigurable logic. IEE Proc. Vol. 147, No. 3. (2000) 175-180
2. Rissa, T., et al.: System-level modeling and implementation technique for run-time reconfigurable systems. Proc. 10th Annual IEEE Symposium on FCCM. (2002) 295-296
3. Vanzago, L., et al.: Design space exploration for a wireless protocol on a reconfigurable platform. Proc. DATE (2003) 662-667
4. Pelkonen, A., et al.: System-Level Modeling of Dynamically Reconfigurable Hardware with SystemC. Proc. IPDPS’03 (2003) 174-181
5. Yang Qu, Soininen, J.-P.: Estimating the utilization of embedded FPGA co-processor. Proc. Euromicro Symposium on DSD. (2003) 214-221