System-level modelling and implementation technique for Run-Time reconfigurable systems

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn 2002-January, Issue , 2002, Pages 295-296

  Rissa, Tero ^a   Vasilko, Milan ^b   Niittylahti, Jarkko ^a  

^a TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

^b BOURNEMOUTH UNIVERSITY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

C++ (PROGRAMMING LANGUAGE); COMPUTERS; HARDWARE; SCHEDULING; STRUCTURAL DESIGN;

HARDWARE-SOFTWARE SYSTEMS; IMPLEMENTATION TECHNIQUES; RUN-TIME RECONFIGURABLE SYSTEMS; SYSTEM COMPONENTS; SYSTEM LEVEL SIMULATION; SYSTEM PARTITION; SYSTEM-LEVEL APPROACH; SYSTEM-LEVEL MODELLING;

COMPUTER HARDWARE;

EID: 84950141062     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPGA.2002.1106690     Document Type: Conference Paper

References (5)

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2. Shaori Guo and Wayne Luk, "Compiling Ruby into FPGAs", in Proc. 5th Int. Workshop on Field-Programmable Logic and Applications, Aug. 1995, pp. 188-197.
3. S. Mostert, N. Cossement, F. Catthoor, J. van Meerbergen, and R. Lauwereins, "DF∗: Modeling dynamic process creation and events for interactive multimedia applications", in Proc. 12th Int. Workshop on Rapid System Prototyping, June 2001, pp. 122-127.
4. Interuniversity Microelectronics Centre, OCAPI-xl Unified modeling and refinement of hardware and software - info sheet, 2000.
5. T. Rissa and J. Niittylahti, "A hybrid prototyping platform for dynamically reconfigurable designs", in Proc. 10th Int. Workshop on Field-Programmable Logic and Applications, Aug. 2000, pp. 371-378.