A hybrid prototyping platform for dynamically reconfigurable designs

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1896, Issue , 2000, Pages 371-378

  Rissa, Tero ^a   Niittylahti, Jarkko ^a  

^a TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; COMPUTER HARDWARE; COMPUTER OPERATING SYSTEMS; DATA HANDLING; DYNAMIC MODELS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MEMORY ARCHITECTURE; PROGRAM DEBUGGING; RECONFIGURABLE ARCHITECTURES;

DESIGN TIME; DYNAMIC RE-CONFIGURATION; FPGA ARCHITECTURES; HYBRID PROTOTYPING; PROTOTYPING PLATFORM; RECONFIGURABILITY; RECONFIGURABLE; RECONFIGURABLE DESIGNS;

RECONFIGURABLE HARDWARE;

EID: 84947583895     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-44614-1_40     Document Type: Conference Paper

References (12)

1. [1] R. W. Hartenstein, “The microprocessor is no longer general purpose: why future reconfigurable platforms will win,” in Proc. 2nd Ann. IEEE Int. Conf. on Innovative Systems in Silicon, Austin, TX, USA, Oct. 8-10 1997, pp. 2-12.
2. [2] Lu Guangming, H. Singh, Lee Ming-Hau, N. Bagherzadeh, F. J. Kurdahi, E. M. C. Filho, and V. Castro-Alves, “The MorphoSys dynamically reconfigurable system-on-chip,” in Proc. 1st NASA/DoD Workshop on Evolvable Hardware, Pasadena, CA, USA, July 19-21 1999, pp. 152-160.
3. [3] S. H.-M. Ludwig, “The design of a coprocessor board using Xilinx's XC6200 FPGA-an experience report,” in Proc. 6th International Workshop on Field-Programmable Logic and Applications, Darmstadt, Germany, Sept. 23-25 1996, pp. 77-86.
4. [4] P. I. MacKinlay, P. Y. K. Cheung, W. Luk, and R. Sandiford, “Riley-2: a flexible platform for codesign and dynamic reconfigurable computing research,” in Proc. 7th Int. Workshop on Field-Programmable Logic and Applications, London, UK, Sept. 1-3 1997, pp. 91-100.
5. [5] M. Vasilko and D. Long, “RIFLE-62: a flexible environment for prototyping dynamically reconfigurable systems,” in Proc. 9th IEEE Int. Workshop on Rapid System Prototyping, Leuven, Belgium, June 3-5 1998, pp. 130-135.
6. [6] G. McGregor, D. Robinson, and P. Lysaght, “A Hardware/Software Co-Design Environment for Reconfigurable Logic Systems,” in Proc. 8th Int. Workshop on Field-Programmable Logic and Applications, Tallinn, Estonia, Aug. 31 - Sept. 3 1998, pp. 259-267.
7. [7] J. Schewel, “A hardware/software co-design system using configurable computing technology,” in Proc. 1st Int. Parallel Processing Symp., Orlando, FL, USA, Mar. 30 - Apr. 3 1996, pp. 620-625.
8. [8] Atmel, Inc., AT40K Series Configuration, Application Note, 1999.
9. [9] Atmel, Inc., AT40K FPGAs with FreeRAM, Databook, 1999.
10. [10] R. Kress, R. W. Hartenstein, and U. Nageldinger, “An operating system for custom computing machines based on the Xputer paradigm,” in Proc. 7th Int. Workshop on Field-Programmable Logic and Applications, London, UK, Sept. 1-3 1997, pp. 304-313.
11. [11] K. S. Chatha and R. Vemuri, “Hardware-software codesign for dynamically reconfigurable architectures,” in Proc. 9th Int. Workshop on Field-Programmable Logic and Applications, Glasgow, UK, Aug. 30 - Sept. 1 1999, pp. 175-184.
12. [12] S. Sezer, J. Heron, R. Woods, R. Turner, and A. Marshall, “Fast partial reconfiguration for FCCMs,” in Proc. IEEE Symp. on FPGAs for Custom Computing Machines, Napa Valley, CA, USA, Apr. 15-17 1998, pp. 318-319.