Verification of dynamically reconfigurable logic

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1896, Issue , 2000, Pages 141-150

  Robinson, David ^a   Lysaght, Patrick ^a  

^a UNIVERSITY OF STRATHCLYDE   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; COMPUTER AIDED DESIGN; MAPPING; RECONFIGURABLE ARCHITECTURES;

COVERAGE ANALYSIS; DESIGN RULE CHECKS; DEVICE RESOURCES; DYNAMIC CIRCUITS; DYNAMICALLY RECONFIGURABLE LOGIC; MANY-TO-ONE; ONE-TO-ONE MAPPINGS; RECONFIGURABLE DESIGNS;

RECONFIGURABLE HARDWARE;

EID: 84947560188     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-44614-1_15     Document Type: Conference Paper

References (10)

1. [1] Avant! Corporation, "Formal Techniques Help Shoulder the Verification Burden" Electronics Journal Technical, Aug. 1998 http://www.avanticorp.com/Avant!/EJ/Technical/Articles/Item/0,1058,88,00.html
2. [2] B. L. Hutchings, "Exploiting Reconfigurability Through Domian-Specific Systems", in Field-Programmable Logic and Applications, W. Luk, P.Y.K. Cheung and M. Glesner (editors), pp. 193-202, London, England, Sept 1997
3. [3] D. Robinson, G. McGregor and P. Lysaght, "New CAD Framework Extends Simulation of Dynamically Reconfigurable Logic", in Field Programmable Logic and Applications, R. Hartenstein and A. Keevallik (Eds.), pp 1-8, Tallinn, Estonia, Sept. 1998
4. [4] P. Lysaght and J. Stockwood, "A Simulation Tool for Dynamically Reconfigurable Field Programmable Gate Arrays", in IEEE Transactions on VLSI Systems, Vol.4, No. 3, pp. 381-390, 1996
5. [5] D. Robinson and P. Lysaght, "Modelling and Synthesis of Configuration Controllers for Dynamically Reconfigurable Logic Systems using the DCS CAD Framework", in Field Programmable Logic and Applications, P. Lysaght, J. Irvine and R. Hartenstein (Eds.), pp 41-50, Glasgow, Scotland, Aug. 1999
6. [6] W. Luk, N. Shirazi and P.Y.K. Cheung, "Modelling and Optimising Run-time Reconfigurable Systems", in IEEE Symposium on Field Programmable Custom Computing Machines, K. L. Pocek and J. Arnold (Eds.), pp. 167-176., Los Alamitos, California, USA, April 1996
7. [7] D. Gibson, M. Vasilko and D. Long, "Virtual Prototyping for Dynamically Reconfigurable Architectures using Dynamic Generic Mapping", in Proceedings of VIUF Fall '98, Orlando, Florida, USA, Oct. 1998
8. [8] M. Vasilko and D. Cabanis, "A Technique for Modelling Dynamic Reconfiguration with Improved Simulation Accuracy", in IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Nov. 1999
9. [9] Gordon Brebner, "CHASTE: a Hardware/Software Co-design Testbed for the Xilinx XC6200", in Reconfigurable Architectures Workshop, R. W. Hartenstein and V. K. Prasanna (Eds.), Geneva, Switzerland, April 1997
10. [10] K. W. Susanto and T. Melham, "Formally Analysed Dynamic Synthesis of Hardware", in Theorem Proving in Higher Order Logics: Emerging Trends: 11th International Conference (TPHOLs'98), Canberra, Australia, Sept. 1998