SCOPUS 정보 검색 플랫폼

Volumn E82-A, Issue 11, 1999, Pages 2465-2474

A technique for modelling dynamic reconfiguration with improved simulation accuracy

Author keywords

Dynamically reconfigurable logic; Fpgas; Logic simulation; Run time reconfiguration; VHDL

Indexed keywords

EID: 33747424052 PISSN: 09168508 EISSN: None Source Type: Journal
DOI: None Document Type: Article

Times cited : (3)

References (12)

1
- 85027124231
- Dynamic reconfiguration of FPGAs
- P. Lysaght and J. DunlopDynamic reconfiguration of FPGAs in More FPGAs eds. W.R. Moore and VV. Luk pp. 82-94 Abingdon EE&CS Books 1994.
- In More FPGAs Eds. W.R. Moore and VV. Luk Pp. 82-94 Abingdon EE&CS Books 1994.
- Lysaght, P.¹ Dunlop, J.²

2
- 0012135454
- VHDL modelling of fast dynamic reconfiguration on novel multicontext RAM-based field programmable devices
- J. Faura J.M. Moreno J. Madrenas and J.M. InsenscrVHDL modelling of fast dynamic reconfiguration on novel multicontext RAM-based field programmable devices Proc. VHDL User's Forum in Europe (VUFE' 97) Toledo Spain April 22-24 1997.
- Proc. VHDL User's Forum in Europe (VUFE' 97) Toledo Spain April 22-24 1997.
- Faura, J.¹ Moreno, J.M.² Madrenas, J.³ Insenscr, J.M.⁴

3
- 0030242765
- A simulation tool for dynamically reconfigurable field programmable gate arrays
- P. Lysaght and J. StockwoodA simulation tool for dynamically reconfigurable field programmable gate arrays IEEE Transactions on VLSI Systems vol. 4 no. 3 pp.381-390 Sept. 1996.
- IEEE Transactions on VLSI Systems Vol. 4 No. 3 Pp.381-390 Sept. 1996.
- Lysaght, P.¹ Stockwood, J.²

4
- 0030414980
- Modelling and optimising run-time reconfigurable systems
- W. Luk N. Shirazi and P.Y.K. CheungModelling and optimising run-time reconfigurable systems Proc. IEEE Symposium on FPGAs for Custom Computing Machines Napa CA USA pp. 167-176 April 17-19 1996.
- Proc. IEEE Symposium on FPGAs for Custom Computing Machines Napa CA USA Pp. 167-176 April 17-19 1996.
- Luk, W.¹ Shirazi, N.² Cheung, P.Y.K.³

5
- 0030388817
- Expressing dynamic reconfiguration by partial evaluation
- S. Singh J. Hogg and D. McAuleyExpressing dynamic reconfiguration by partial evaluation Proc. IEEE Symposium on FPGAs for Custom Computing Machines Napa CA USA pp. 188-194 April 17-19 1996.
- Proc. IEEE Symposium on FPGAs for Custom Computing Machines Napa CA USA Pp. 188-194 April 17-19 1996.
- Singh, S.¹ Hogg, J.² McAuley, D.³

6
- 85027140554
- Virtual prototyping for dynamically rcconfigurable systems
- D. Gibson M. Vasilko and D. LongVirtual prototyping for dynamically rcconfigurable systems Proc. VUIF Fall ' 98 Orlando Florida USA Oct. 26-28 1998.
- Proc. VUIF Fall ' 98 Orlando Florida USA Oct. 26-28 1998.
- Gibson, D.¹ Vasilko, M.² Long, D.³

7
- 85027153721
- D. Robinson and P. Lysaght Dynamic circuit switching E-mail communication April-May 1999.
- Robinson, D.¹ Lysaght, P.² Switching, D.C.³ Communication, E.-M.⁴

8
- 84957882077
- W. Luk N. Shirazi S.R. Guo and P.Y.K. CheungPipeline morphing and virtual pipelines in Field Programmable Logic and Applications cds. W. Luk P.Y.K. Cheung and M. Glesner pp. 111-120 LNCS 1304 Springer-Verlag 1997.
- Pipeline morphing and virtual pipelines
- Luk, W.¹ Shirazi, N.² Guo, S.R.³ Cheung, P.Y.K.⁴

9
- 85027195877
- IEEE IEEE Std 1076-1987 IEEE Standard VHDL Reference Manual 1987.
- IEEE IEEE Std 1076-1987 IEEE Standard VHDL Reference Manual 1987.

10
- 85027165000
- Xilinx Inc. XC 6200 Field Programmable Gate Arrays Advanced Product Information Version 1.10 April 1997.
- Xilinx¹

11
- 85027108871
- IEEE IEEE Standard Multivalue Logic System for VHDL Model Interoperability (StdJogic. 1164) May 26 1993.
- Pipeline morphing and virtual pipelines
- Luk, W.¹ Shirazi, N.² Guo, S.R.³ Cheung, P.Y.K.⁴

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.