Automatic temporal floorplanning with guaranteed solution feasibility

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1896, Issue , 2000, Pages 656-664

  Vasilko, Milan ^a   Benyon Tinker, Graham ^a  

^a BOURNEMOUTH UNIVERSITY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; COMPUTATION THEORY; COMPUTER PROGRAMMING; RECONFIGURABLE ARCHITECTURES;

AUTOMATIC DESIGN SYNTHESIS; AUTOMATICALLY GENERATED; DYNAMICALLY RECONFIGURABLE LOGIC; MULTIPLE-OBJECTIVES; PARTIAL RECONFIGURATION; RECONFIGURATION OVERHEAD; SYNTHESIS ALGORITHMS; TEMPORAL FLOORPLANNING;

RECONFIGURABLE HARDWARE;

EID: 84947546792     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-44614-1_70     Document Type: Conference Paper

References (12)

1. M. Vasilko and D. Ait-Boudaoud, “Architectural synthesis techniques for dynamically reconfigurable logic,” in Hartenstein and Glesner [12], pp. 290–296.
2. M. Kaul and R. Vemuri, “Optimal temporal partitioning and synthesis for reconfigurable architectures,” in Design, Automation and Test in Europe Conference, (Paris, France), Feb. 23–26, 1998.
3. K. M. GajjalaPurna and D. Bhatia, “Temporal partitioning and scheduling for reconfigurable computing,” (Napa, CA), pp. 329–330, Apr. 15–17, 1998.
4. K. Bazargan, R. Kaster, and M. Sarrafzadeh, “3-D floorplanning: Simulated annealing and greedy placement methods for reconfigurable computing systems,” in Proceedings of the IEEE Workshop on Rapid System Prototyping (RSP’99), (Clearwater, FL, USA), June 16–18, 1999.
5. M. Vasilko, “DYNASTY: A temporal floorplanning based CAD framework for dynamically reconfigurable logic systems,” in Field-Programmable Logic and Applications (P. Lysaght, J. Irvine, and R. Hartenstein, eds.), LNCS 1673, (Glasgow, UK), pp. 124–133, Springer-Verlag, Aug. 30–Sept. 1, 1999.
6. D. E. Goldberg, Genetic Algorithms in Search, Optimisation, and Machine Learning. Addison-Wesley, 1989.
7. M. Wall, GAlib: A C++ Library of Generic Algorithm Components, version 2.4. MIT, available from http://lancet.mit.edu/ga/, Aug. 1996.
8. Xilinx, XC6200 Field Programmable Gate Arrays. Xilinx, Inc., Apr. 1997. Version 1.10.
9. P. G. Paulin and J. P. Knight, “Algorithms for high-level synthesis,” IEEE Design and Test of Computers, vol. 6, pp. 18–31, Dec. 1989.
10. J. P. Heron and R. F. Woods, “Architectural strategies for implementing an image processing algorithm on XC6200 FPGA,” in Hartenstein and Glesner [12], pp. 317–326.
11. P. Foulk and I. Hodson, “Data folding in SRAM configurable FPGAs,” in IEEE Workshop on FPGAs for Custom Computing Machines (D. A. Buell and K. L. Pocek, eds.), Napa, CA, USA: IEEE Comput. Soc. Press, Apr. 5–7, 1993.
12. R. W. Hartenstein and M. Glesner, eds., Field-Programmable Logic: Smart Applications, New Paradigms and Compilers, (FPL’96 Proceedings), LNCS 1142, Springer-Verlag, 1996.