Using incorrect speculation to prefetch data in a concurrent multithreaded processor

Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003

Volumn , Issue , 2003, Pages

  Chen, Ying ^a   Sendag, Resit ^a   Lilja, David J ^a  

^a University of Minnesota   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; BUFFER STORAGE; COMPUTER ARCHITECTURE; DISTRIBUTED PARAMETER NETWORKS; LEVEL CONTROL; MEMORY ARCHITECTURE; MICROPROCESSOR CHIPS;

BENCHMARK PROGRAMS; INSTRUCTION-LEVEL; MISPREDICTED LOADS; MULTITHREADED ARCHITECTURE; MULTITHREADED PROCESSORS; POTENTIAL POLLUTIONS; THREAD LEVEL PARALLELISM; WRONG EXECUTION CACHE;

CONCURRENCY CONTROL;

EID: 84947279167     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2003.1213177     Document Type: Conference Paper

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