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Volumn , Issue , 1996, Pages 666-671
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Integrating formal verification methods with a conventional project design flow
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Author keywords
[No Author keywords available]
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Indexed keywords
BUFFER STORAGE;
CRITICAL PATH ANALYSIS;
DISTRIBUTED COMPUTER SYSTEMS;
FINITE AUTOMATA;
HIGH LEVEL LANGUAGES;
MATHEMATICAL MODELS;
NETWORK PROTOCOLS;
REAL TIME SYSTEMS;
STORAGE ALLOCATION (COMPUTER);
TIME SHARING SYSTEMS;
CACHE COHERENCE;
TEMPORAL LOGIC MODEL CHECKER;
LOGIC DESIGN;
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EID: 0029699367
PISSN: 0738100X
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1145/240518.240644 Document Type: Conference Paper |
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Times cited : (13)
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References (0)
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