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Volumn 2015-April, Issue , 2015, Pages 884-887

SODA: Software defined FPGA based accelerators for big data

Author keywords

Acceleratioin; Big data; FPGA; Software defined

Indexed keywords

APPLICATION PROGRAMS; ENERGY EFFICIENCY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); LINEAR ACCELERATORS;

EID: 84945963776     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.7873/date.2015.0536     Document Type: Conference Paper
Times cited : (39)

References (16)
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    • Andrew Putnam, Adrian M. Caulfield, et al. A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services. in ISCA. 2014
    • (2014) ISCA
    • Putnam, A.1    Caulfield, A.M.2
  • 4
    • 70749153686 scopus 로고    scopus 로고
    • Factored operating systems (fos): The case for a scalable operating system for multicores
    • David Wentzlaff and Anant Agarwal, Factored operating systems (fos): the case for a scalable operating system for multicores. ACM SIGOPS Operating Systems Review, 2009. 43(2): p. 76-85
    • (2009) ACM SIGOPS Operating Systems Review , vol.43 , Issue.2 , pp. 76-85
    • Wentzlaff, D.1    Agarwal, A.2
  • 6
    • 84903195407 scopus 로고    scopus 로고
    • CGPA: Coarse-grained pipelined accelerators
    • ACM: San Francisco, CA, USA
    • Feng Liu, Soumyadeep Ghosh, et al., CGPA: Coarse-Grained Pipelined Accelerators, in 51st Design Automation Conference. 2014, ACM: San Francisco, CA, USA
    • (2014) 51st Design Automation Conference
    • Liu, F.1    Ghosh, S.2
  • 7
    • 84862705598 scopus 로고    scopus 로고
    • Investigation into scaling I/O bound streaming applications productively with an all-FPGA cluster
    • Andrew G. Schmidt, Siddhartha Datta, et al., Investigation into scaling I/O bound streaming applications productively with an all-FPGA cluster. Parallel Computing, 2012. 38(8): p. 344-364
    • (2012) Parallel Computing , vol.38 , Issue.8 , pp. 344-364
    • Schmidt, A.G.1    Datta, S.2
  • 13
    • 4644281774 scopus 로고    scopus 로고
    • Programming models for hybrid FPGA-cpu computational components: A missing link
    • David L. Andrews, Douglas Niehaus, et al., Programming models for hybrid FPGA-cpu computational components: a missing link. IEEE Micro, 2004. 24(4): p. 42-53
    • (2004) IEEE Micro , vol.24 , Issue.4 , pp. 42-53
    • Andrews, D.L.1    Niehaus, D.2
  • 14
    • 40549129379 scopus 로고    scopus 로고
    • A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH
    • Hayden Kwok-Hay So and Robert W. Brodersen, A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH. ACM Trans. Embedded Comput. Syst., 2008. 7(2)
    • (2008) ACM Trans. Embedded Comput. Syst , vol.7 , Issue.2
    • Kwok-Hay, S.H.1    Brodersen, R.W.2
  • 15
  • 16
    • 84908058840 scopus 로고    scopus 로고
    • Architecture support for task out-of-order execution in MPSoCs
    • Chao Wang, Xi Li, et al., Architecture Support for Task Out-of-order Execution in MPSoCs. IEEE Transactions on Computers, 2014
    • (2014) IEEE Transactions on Computers
    • Wang, C.1    Li, X.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.