Programming models for hybrid FPGA-CPU computational components: A missing link

IEEE Micro

Volumn 24, Issue 4, 2004, Pages 42-53

  Andrews, David ^a   Niehaus, Douglas ^a   Jidin, Razali ^b   Finley, Michael ^a   Peck, Wesley ^b   Frisbie, Michael ^c   Ortiz, Jorge ^a   Komp, Ed ^b   Ashenden, Peter ^d  

^a University of Kansas   (United States)

^b UNIVERSITY OF KANSAS   (United States)

^c Garmin International Inc   (United States)

^d Ashenden Designs   (Australia)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER OPERATING SYSTEMS; COMPUTER PROGRAMMING LANGUAGES; EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS; REAL TIME SYSTEMS; REQUIREMENTS ENGINEERING; SOFTWARE ENGINEERING; SYSTEMS ANALYSIS;

HARDWARE CUSTOMIZATION; HYBRID CHIPS; MULTITHREADED PROGRAMMING MODEL;

MICROPROCESSOR CHIPS;

EID: 4644281774     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2004.36     Document Type: Article

References (12)

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