HiBRID-SoC: A system-on-chip architecture with two multimedia DSPs and a RISC core

Proceedings - IEEE International SOC Conference, SOCC 2003

Volumn , Issue , 2003, Pages 85-88

  Friebe, L ^a   Stolberg, H J ^a   Berekovic M ^a   Moch, S ^a   Kulaczewski, M B ^a   Dehnhardt, A ^a   Pirsch, R ^a  

^a LEIBNIZ UNIVERSITY HANNOVER   (Germany)

Author keywords

Application software; Computer architecture; Digital signal processing; Hardware; MPEG 4 Standard; Multimedia systems; Reduced instruction set computing; Streaming media; System buses; System on a chip

Indexed keywords

ALGORITHMS; APPLICATION PROGRAMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; DIGITAL SIGNAL PROCESSING; DYNAMIC RANDOM ACCESS STORAGE; MEDIA STREAMING; MICROPROCESSOR CHIPS; MOTION PICTURE EXPERTS GROUP STANDARDS; MULTIMEDIA SYSTEMS; PROGRAM PROCESSORS; PROGRAMMABLE LOGIC CONTROLLERS; RANDOM ACCESS STORAGE; REDUCED INSTRUCTION SET COMPUTING; SIGNAL PROCESSING; SYSTEM BUSES;

CONTROL INFORMATION; DUAL-PORT MEMORY; FULLY PROGRAMMABLES; MPEG-4 STANDARD; STREAM PROCESSOR; STREAMING MEDIA; SYSTEM ON A CHIP; SYSTEM-ON-CHIP ARCHITECTURE;

SYSTEM-ON-CHIP;

EID: 84945381829     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOC.2003.1241468     Document Type: Conference Paper

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