High velociTI processing

IEEE Signal Processing Magazine

Volumn 15, Issue 2, 1998, Pages 86-101

  Seshan, Nat ^a   Sites, Web ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CRITICAL PATH ANALYSIS; MICROPROCESSOR CHIPS; PARALLEL PROCESSING SYSTEMS; PIPELINE PROCESSING SYSTEMS; PROGRAM COMPILERS; REDUCED INSTRUCTION SET COMPUTING;

CENTRAL PROCESSING UNIT (CPU); VERY LONG INSTRUCTION WORD (VLIW) ARCHITECTURE;

DIGITAL SIGNAL PROCESSING;

EID: 0032022814     PISSN: 10535888     EISSN: None     Source Type: Journal    
DOI: 10.1109/79.664702     Document Type: Article

References (7)

1. J.A. Fisher, Very Long Instruction Word Architectures. 253, Yale University, 1983.
2. M. Lam, Software Pipelining: An effective scheduling technique for VLIW machines. SIGPLAN '88 Conference on Programming Language Design and Implementation, June 1988, pp. 318-328.
3. A. Davis, E. Stotzer, R. Targe, and A. Ward, Approaching Peak Performance with Compiled Code on a VLIW DSP, July 1997, Texas Instruments.
4. D.A. Patterson and D.R. Ditzel, The case for the reduced instruction set computer. Computer Architecture News 8(6), October 1980, pp. 25-33.
5. P. Lapsley, J. Bier, A. Shohan, and E.A. Lee, DSP Processor fundamentals - Architectures and Features, Berkeley Design Technology, Inc., 1996.
6. R. Scales, Approaching Optimal Performance with the C62x Assembly Optimizer, October 1997, Texas Instruments.
7. T.J. Dillon, The Use of Software Pipelining in Developing DSP Algorithms for the TMS320C6x, Proceedings of the International Conference on Signal Processing & Technology, Sept. 1997.