A novel collector-tub concept for realizing high-voltage lateral bipolar transistors on SOI

Proceedings of the International Conference on Microelectronics, ICM

Volumn 2003-January, Issue , 2003, Pages 336-339

  Jagadesh Kumar, M ^a   Roy, S D ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

Author keywords

Annealing; Avalanche breakdown; Bipolar transistors; Breakdown voltage; Doping profiles; Etching; Insulation; Semiconductor process modeling; Silicon on insulator technology; Substrates

Indexed keywords

ANNEALING; BIPOLAR TRANSISTORS; ELECTRIC BREAKDOWN; ELECTRIC FIELDS; ELECTRIC INSULATORS; ETCHING; HETEROJUNCTION BIPOLAR TRANSISTORS; INSULATION; MICROELECTRONICS; SEMICONDUCTING SILICON; SEMICONDUCTOR DOPING; SEMICONDUCTOR JUNCTIONS; SUBSTRATES; TRANSISTORS;

AVALANCHE BREAKDOWN; COLLECTOR EMITTER BREAKDOWN; DOPING PROFILES; ELECTRIC FIELD PROFILES; LATERAL BIPOLAR TRANSISTORS; SEMICONDUCTOR PROCESS MODELING; SILICON-ON- INSULATORS (SOI); TWO-DIMENSIONAL NUMERICAL SIMULATION;

SILICON ON INSULATOR TECHNOLOGY;

EID: 84945299624     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICM.2003.237927     Document Type: Conference Paper

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