Reducing memory latency via non-blocking and prefetching caches

International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS

Volumn 27, Issue 9, 1992, Pages 51-61

  Chen, Tien Fu ^a   Baer, Jean Loup ^a  

^a UNIVERSITY OF WASHINGTON   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SYSTEMS; DESIGN; PROGRAM COMPILERS; SIMULATION; STORAGE ALLOCATION (COMPUTER);

MEMORY LATENCY; NON-BLOCKING CACHES; PREFETCHING CACHES;

DATA STORAGE EQUIPMENT; COMPUTER HARDWARE;

HARDWARE-BASED SCHEMES; MEMORY LATENCY REDUCTION; NONBLOCKING CACHES; PREFETCHING CACHE;

EID: 0026917364     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/143371.143486     Document Type: Conference Paper

References (16)