Improving formal timing analysis of switched ethernet by exploiting FIFO scheduling

Proceedings - Design Automation Conference

Volumn 2015-July, Issue , 2015, Pages

  Thiele, Daniel ^a   Axer, PhilIP ^a   Ernst, Rolf ^a  

^a TECHNICAL UNIVERSITY OF BRAUNSCHWEIG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ADVANCED DRIVER ASSISTANCE SYSTEMS; AUTOMOBILE DRIVERS; COMPUTER AIDED DESIGN; ETHERNET; INTERACTIVE COMPUTER SYSTEMS; SAFETY ENGINEERING; SCHEDULING; TIMING CIRCUITS;

AUTOMOTIVE CONTROL; AUTOMOTIVE DOMAINS; EMERGING TECHNOLOGIES; END TO END LATENCIES; PERFORMANCE ANALYSIS; SWITCHED ETHERNET; TIMING ANALYSIS; UPPER BOUND;

REAL TIME SYSTEMS;

EID: 84944128121     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2744769.2744854     Document Type: Conference Paper

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