Correctness and security at odds: Post-silicon validation of modern SoC designs

Proceedings - Design Automation Conference

Volumn 2015-July, Issue , 2015, Pages

  Ray, SandIP ^a   Yang, Jin ^a   Basak, Abhishek ^b   Bhunia, Swarup ^b  

^a INTEL CORPORATION   (United States)

^b CASE WESTERN RESERVE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; ECONOMIC AND SOCIAL EFFECTS; SILICON; SYSTEM-ON-CHIP; COMPUTER ARCHITECTURE; DESIGN;

POST-SILICON VALIDATIONS; SECURITY VULNERABILITIES; SOC DESIGNS; STATE OF THE PRACTICE; TRADE OFF;

COMPUTER ARCHITECTURE; SILICON;

EID: 84944080757     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2744769.2754896     Document Type: Conference Paper

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