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Volumn , Issue , 2013, Pages 384-389

Scalable trace signal selection using machine learning

Author keywords

machine learning; Post silicon; signal selection

Indexed keywords

SILICON;

EID: 84892518916     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2013.6657069     Document Type: Conference Paper
Times cited : (16)

References (16)
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    • Basu, K.1    Mishra, P.2
  • 2
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    • Basu, K.1    Mishra, P.2    Patra, P.3
  • 3
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    • Chang, C.-C.1    Lin, C.-J.2
  • 4
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    • Simulation-based signal selection for state restoration in silicon debug
    • D. Chatterjee et al. Simulation-based signal selection for state restoration in silicon debug. In ICCAD, 2011.
    • (2011) ICCAD
    • Chatterjee, D.1
  • 5
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    • Delay fault testing and silicon debug using scan chains
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    • Algorithms for state restoration and trace-signal selection for data acquisition in silicon debug
    • H. F. Ko and N. Nicolici. Algorithms for state restoration and trace-signal selection for data acquisition in silicon debug. TCAD, 2009.
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    • Ko, H.F.1    Nicolici, N.2
  • 7
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    • Combining scan and trace buffers for enhancing real-time observability in post-silicon debugging
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    • Ko, H.F.1    Nicolici, N.2
  • 8
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    • A hybrid approach for fast and accurate trace signal selection for post-silicon debug
    • M. Li and A. Davoodi. A hybrid approach for fast and accurate trace signal selection for post-silicon debug. In DATE, 2013.
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    • Li, M.1    Davoodi, A.2
  • 9
    • 70350062059 scopus 로고    scopus 로고
    • Trace signal selection for visibility enhancement in post-silicon validation
    • X. Liu and Q. Xu. Trace signal selection for visibility enhancement in post-silicon validation. In DATE, 2009.
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    • Liu, X.1    Xu, Q.2
  • 10
    • 77956195816 scopus 로고    scopus 로고
    • Bridging pre-silicon verification and post-silicon validation
    • A. Nahir et al. Bridging pre-silicon verification and post-silicon validation. In DAC, 2010.
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  • 11
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  • 12
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    • Efficient signal selection using fine-grained combination of scan and trace buffers
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    • Rahmani, K.1    Mishra, P.2
  • 13
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    • Trace signal selection to enhance timing and logic visibility in post-silicon validation
    • H. Shojaei and A. Davoodi. Trace signal selection to enhance timing and logic visibility in post-silicon validation. In ICCAD, 2010.
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    • Shojaei, H.1    Davoodi, A.2
  • 15
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  • 16
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.