Hardware implementation of the binary method for exponentiation in GF(2m)

Proceedings of the Mexican International Conference on Computer Science

Volumn 2003-January, Issue , 2003, Pages 131-134

  Garcia Martinez M A ^a   Morales Luna, G ^b   Rodriguez Henriquez F ^b  

^a INSTITUTO TECNOLÓGICO DE ORIZABA   (Mexico)

^b DEPARTAMENTO DE FÍSICA   (Mexico)

Author keywords

Application specific integrated circuits; Computer architecture; Cryptography; Digital signal processing; Field programmable gate arrays; Galois fields; Hardware; Security; Signal processing algorithms; Software performance

Indexed keywords

ALGORITHMS; APPLICATION PROGRAMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; BINS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; CRYPTOGRAPHY; DIGITAL INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSING; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; INTEGRATED CIRCUITS; LOGIC GATES; SIGNAL PROCESSING;

CRYPTOGRAPHIC ALGORITHMS; ERROR CORRELATION; GALOIS FIELDS; HARDWARE IMPLEMENTATIONS; HARDWARE RESOURCES; SECURITY; SIGNAL PROCESSING ALGORITHMS; SOFTWARE PERFORMANCE;

COMPUTER HARDWARE;

EID: 84942934238     PISSN: 15504069     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ENC.2003.1232886     Document Type: Conference Paper

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